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{{ic family | {{ic family | ||
| title = Intel Core i5 | | title = Intel Core i5 | ||
− | | image = core i5 logo | + | | image = core i5 logo.png |
| image size = 150px | | image size = 150px | ||
| caption = Core i5 Logo | | caption = Core i5 Logo | ||
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| microarch 6 = Broadwell | | microarch 6 = Broadwell | ||
| microarch 7 = Skylake | | microarch 7 = Skylake | ||
− | | microarch 8 = Kaby | + | | microarch 8 = Kaby Lakee |
| microarch 9 = Coffee Lake | | microarch 9 = Coffee Lake | ||
| microarch 10 = Ice Lake | | microarch 10 = Ice Lake | ||
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== 4th Generation (Haswell) == | == 4th Generation (Haswell) == | ||
− | {{main|intel/microarchitectures/haswell|l1=Haswell Microarchitecture}} | + | {{main|intel/microarchitectures/haswell|l1=Haswell Microarchitecture}} |
{{empty section}} | {{empty section}} | ||
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− | ==== | + | ==== Mobile ==== |
{{see also|intel/cores/skylake u|intel/cores/skylake u|l1=Skylake U|l2=Skylake Y}} | {{see also|intel/cores/skylake u|intel/cores/skylake u|l1=Skylake U|l2=Skylake Y}} | ||
Mobile {{intel|Skylake|l=arch}}-based Mid-range processors were introduced in late [[2015]]. Mobile Core i5 uses {{intel|FCLGA-1515}}/{{intel|FCLGA-1356}} sockets which incorporate the chipset as well as the microprocessor itself in the same package. | Mobile {{intel|Skylake|l=arch}}-based Mid-range processors were introduced in late [[2015]]. Mobile Core i5 uses {{intel|FCLGA-1515}}/{{intel|FCLGA-1356}} sockets which incorporate the chipset as well as the microprocessor itself in the same package. | ||
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<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19"> | <table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19"> | ||
− | <tr class="comptable-header"><th> </th><th colspan="12">List of Skylake-based Core i5 | + | <tr class="comptable-header"><th> </th><th colspan="12">List of Skylake-based Core i5 Mobile Processors</th></tr> |
<tr class="comptable-header"><th> </th><th colspan="8">Main processor</th><th colspan="3">IGP</th></tr> | <tr class="comptable-header"><th> </th><th colspan="8">Main processor</th><th colspan="3">IGP</th></tr> | ||
{{comp table header 1|cols=Price, Process, Launched, C, T, Freq, TDP, Max Mem, Name, Freq, Turbo Freq}} | {{comp table header 1|cols=Price, Process, Launched, C, T, Freq, TDP, Max Mem, Name, Freq, Turbo Freq}} | ||
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− | == 8th Generation | + | == 8th Generation (Kaby Lake Refresh) == |
− | + | [[File:8th gen core i5 logo.png|right|150px]] | |
− | + | === Mobile === | |
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− | === Mobile | ||
In August [[2017]] Intel introduced 8th generation mobile Core i5 processors. Contrary to their namesake, those initial chips were still based on the same {{intel|Kaby Lake|l=arch}} microarchitecture as 7th generation. Those new microprocessors do bring some considerable performance increase in both [[single thread]] and more significantly in [[multi-threaded]] applications due to Intel doubling the number of [[physical core|cores]] from [[dual-core|2]] to [[quad-core|4]] while maintaining roughly the same price as previous generation. All mobile models still use soldered {{intel|BGA-1356}} socket and as with previous generation, those new mobile Core i5 chip also have {{intel|Hyper-Threading}} enabled, providing 8 threads for all models. | In August [[2017]] Intel introduced 8th generation mobile Core i5 processors. Contrary to their namesake, those initial chips were still based on the same {{intel|Kaby Lake|l=arch}} microarchitecture as 7th generation. Those new microprocessors do bring some considerable performance increase in both [[single thread]] and more significantly in [[multi-threaded]] applications due to Intel doubling the number of [[physical core|cores]] from [[dual-core|2]] to [[quad-core|4]] while maintaining roughly the same price as previous generation. All mobile models still use soldered {{intel|BGA-1356}} socket and as with previous generation, those new mobile Core i5 chip also have {{intel|Hyper-Threading}} enabled, providing 8 threads for all models. | ||
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* '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | * '''ISA:''' Everything up to AVX2 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, and AVX2) | ||
* '''Tech:''' {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|Turbo Boost}} 2.0, {{intel|VT-x}}, {{intel|VT-d}}/{{intel|EPT}}, {{intel|TSX}}, {{intel|Flex Memory}}, {{intel|Smart Response}}, {{intel|My WiFi}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|Secure Key}} | * '''Tech:''' {{intel|SpeedStep}}, {{intel|Speed Shift}}, {{intel|Turbo Boost}} 2.0, {{intel|VT-x}}, {{intel|VT-d}}/{{intel|EPT}}, {{intel|TSX}}, {{intel|Flex Memory}}, {{intel|Smart Response}}, {{intel|My WiFi}}, Software Guard ({{intel|SGX}}), Memory Protection ({{intel|MPX}}), {{intel|OS Guard}}, {{intel|Secure Key}} | ||
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This table is generated automatically from the data in the actual articles. | This table is generated automatically from the data in the actual articles. | ||
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− | == | + | == 9th Generation (Ice Lake) == |
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/ice lake|l1=Ice Lake Microarchitecture}} |
− | + | 9th generation Core i3 processors are manufactured on Intel's 2nd generation enhanced [[10 nm process|10nm+ process]] and are based on their {{intel|Ice Lake|l=arch}} microarchitecture. | |
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=== Desktop === | === Desktop === | ||
− | {{ | + | {{future information}} |
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− | Missing a chip? please dump its name here: | + | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips |
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable"> | + | <table class="comptable sortable tc4"> |
− | {{comp table header|main| | + | {{comp table header|main|8:List of Ice Lake-based Desktop Core i5 Processors}} |
− | {{comp table header|main|7:Main processor| | + | {{comp table header|main|7:Main processor|1:IGP}} |
− | {{comp table header|cols|Price|Launched|Cores|Threads| | + | {{comp table header|cols|Market|Price|Launched|%Frequency|Cores|Threads|Max Mem|Name}} |
− | {{#ask: [[Category:microprocessor models by intel]] [[ | + | {{#ask: [[Category:microprocessor models by intel]] [[family::Core i5]] [[microarchitecture::Ice Lake]] [[market segment::Desktop]] |
|?full page name | |?full page name | ||
|?model number | |?model number | ||
+ | |?market segment | ||
|?release price | |?release price | ||
|?first launched | |?first launched | ||
+ | |?base frequency#GHz | ||
|?core count | |?core count | ||
|?thread count | |?thread count | ||
− | |? | + | |?max memory#GiB |
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|?integrated gpu | |?integrated gpu | ||
− | |? | + | |?isa |
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|format=template | |format=template | ||
|template=proc table 3 | |template=proc table 3 | ||
− | |userparam= | + | |userparam=10 |
|mainlabel=- | |mainlabel=- | ||
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}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by intel]] [[ | + | {{comp table count|ask=[[Category:microprocessor models by intel]] [[family:Core i5]] [[microarchitecture::Ice Lake]] [[market segment::Desktop]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
− | + | {{DEFAULTSORT:Core i5, Intel}} | |
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− | {{ | ||
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== See also == | == See also == | ||
{{intel core see also}} | {{intel core see also}} |
Facts about "Core i5 - Intel"
designer | Intel + |
first announced | June 17, 2009 + |
first launched | September 2009 + |
full page name | intel/core i5 + |
instance of | microprocessor family + |
instruction set architecture | IA-32 + and x86-64 + |
main designer | Intel + |
manufacturer | Intel + |
microarchitecture | Nehalem +, Westmere +, Sandy Bridge +, Ivy Bridge +, Haswell +, Broadwell +, Skylake +, Kaby Lake +, Coffee Lake + and Ice Lake + |
name | Intel Core i5 + |
package | FCBGA-1440 +, FCBGA-1364 +, FCBGA-1288 +, FCBGA-1168 +, FCLGA-1155 +, FCLGA-1151 +, FCLGA-1150 +, FCBGA-1023 +, FCPGA-988 + and FCPGA-946 + |
process | 45 nm (0.045 μm, 4.5e-5 mm) +, 32 nm (0.032 μm, 3.2e-5 mm) +, 22 nm (0.022 μm, 2.2e-5 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-1151 +, LGA-1150 +, LGA-1155 +, LGA-1156 +, Socket G1 +, Socket G2 + and Socket G3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |