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Difference between revisions of "intel/celeron/b800"
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== Documents ==
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=== Datasheet ===
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* [[:File:2nd-gen-core-family-mobile-vol-1-datasheet.pdf|Datasheet, Volume 1]]
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* [[:File:2nd-gen-core-family-mobile-vol-2-datasheet.pdf|Datasheet, Volume 2]]
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=== Other ===
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* [[:File:2nd-gen-core-mobile-thermal-guide.pdf|Thermal Design Guide for Embedded Applications]]
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* [[:File:2nd-gen-core-family-mobile-specification-update.pdf|2nd Gen Core Mobile Specification Update]]

Revision as of 15:33, 20 August 2017

Template:mpu Celeron B800 is a dual-core budget mobile x86 microprocessor introduced by Intel in mid-2011. The Celeron B800, which is based on the Sandy Bridge microarchitecture and is manufactured on a 32 nm process, operates at 1.5 GHz with a TDP of 35 W. This chip incorporates Intel's HD Graphics integrated graphics operating at 650 MHz with a bust frequency of 1 GHz. This processor supports 16 GiB of dual-channel DDR3-1333 memory.

Cache

Main article: Sandy Bridge § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
2x32 KiB8-way set associativewrite-back
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  2x256 KiB8-way set associativewrite-back
L3$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  2x1 MiB8-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR3-1333, DDR3-1066
Supports ECCNo
Max Mem16 GiB
Controllers1
Channels2
Max Bandwidth19.87 GiB/s
20,346.88 MiB/s
21.335 GB/s
21,335.25 MB/s
0.0194 TiB/s
0.0213 TB/s
Bandwidth
Single 9.93 GiB/s
Double 19.87 GiB/s

Expansions

[Edit/Modify Expansions Info]

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Expansion Options
PCIeRevision: 2.0
Max Lanes: 16
Configuration: 1x16, 2x8, 1x8+2x4


Graphics

[Edit/Modify IGP Info]

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Integrated Graphics Information
GPUHD Graphics (Sandy Bridge)
DesignerIntelDevice ID0x0106
Execution Units6Max Displays2
Frequency650 MHz
0.65 GHz
650,000 KHz
Burst Frequency1,000 MHz
1 GHz
1,000,000 KHz
OutputDP, eDP, HDMI, SDVO, CRT
Standards
DirectX10.1
OpenGL3.1
DP1.1
eDP1.1
HDMI1.4
Additional Features
Intel Flexible Display Interface (FDI)

Features

Documents

Datasheet

Other

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/celeron/b800&oldid=61637"
Facts about "Celeron B800 - Intel"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Celeron B800 - Intel#pcie +
device id0x0106 +
has ecc memory supportfalse +
has featureIntel VT-x + and Flex Memory Access +
has intel flex memory access supporttrue +
has intel vt-x technologytrue +
integrated gpuHD Graphics (Sandy Bridge) +
integrated gpu base frequency650 MHz (0.65 GHz, 650,000 KHz) +
integrated gpu designerIntel +
integrated gpu execution units6 +
integrated gpu max frequency1,000 MHz (1 GHz, 1,000,000 KHz) +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description8-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description8-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l3$ description8-way set associative +
l3$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
max memory bandwidth19.87 GiB/s (20,346.88 MiB/s, 21.335 GB/s, 21,335.25 MB/s, 0.0194 TiB/s, 0.0213 TB/s) +
max memory channels2 +
supported memory typeDDR3-1333 + and DDR3-1066 +