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Difference between revisions of "intel/atom/c3558"
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== Memory controller ==
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{{memory controller}}

Revision as of 23:23, 15 August 2017

Template:mpu Atom C3558 is a 64-bit quad-core ultra-low power x86 microserver system on a chip introduced by Intel in 2017. The C3558, which is manufactured on a 14 nm process, is based on the Goldmont microarchitecture. This chip operates at 2.2 GHz with a TDP of 16 W. The C3558 supports up to a dual-channel of 256 GiB of DDR4-1866 ECC memory.

Cache

Main article: Goldmont § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$224 KiB
229,376 B
0.219 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associativewrite-back
L1D$96 KiB
98,304 B
0.0938 MiB
4x24 KiB6-way set associativewrite-back

L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  4x2 MiB16-way set associativewrite-back

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Facts about "Atom C3558 - Intel"
has ecc memory supportfalse +
l1$ size224 KiB (229,376 B, 0.219 MiB) +
l1d$ description6-way set associative +
l1d$ size96 KiB (98,304 B, 0.0938 MiB) +
l1i$ description8-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +