From WikiChip
Difference between revisions of "ibm/poweraxon"
< ibm

Line 1: Line 1:
 
{{ibm title|PowerAXON}}
 
{{ibm title|PowerAXON}}
'''PowerAXON''' is a marketing term used by [[IBM]] to describe a collection of high-speed I/O [[interconnect architecture|interconnects]] used by their {{ibm|POWER9|l=arch}} platform. ''PowerAXON'' stands for '''Power''' with [[A-bus|'''A'''-bus]], [[X-bus|'''X'''-bus]], [[OpenCAPI|'''O'''penCAPI]], and [[NVLink|'''N'''VLink]].
+
'''PowerAXON''' is a marketing term used by [[IBM]] to describe a collection of high-speed I/O [[interconnect architecture|interconnects]] used by their {{ibm|POWER9|l=arch}} platform. ''PowerAXON'' stands for '''Power''' with [[A-bus|'''A'''-bus]], [[X-bus|'''X'''-bus]], [[OpenCAPI|'''O'''penCAPI]], and [[NVLink|'''N'''VLink]]. Those interconnects operate at a signaling rate of 25 GT/s.
  
 
[[category:ibm]]
 
[[category:ibm]]

Revision as of 01:09, 28 September 2018

PowerAXON is a marketing term used by IBM to describe a collection of high-speed I/O interconnects used by their POWER9 platform. PowerAXON stands for Power with A-bus, X-bus, OpenCAPI, and NVLink. Those interconnects operate at a signaling rate of 25 GT/s.