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Latest revision | Your text | ||
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|introduction=September 12, 2019 | |introduction=September 12, 2019 | ||
|process=14 nm | |process=14 nm | ||
− | |cores | + | |cores=12 |
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|type=Superscalar | |type=Superscalar | ||
|type 2=Pipelined | |type 2=Pipelined | ||
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|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
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|isa=z/Architecture | |isa=z/Architecture | ||
|l1i=128 KiB | |l1i=128 KiB | ||
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! Feature<br>Code !! Feature<br>Name !! CPC Drawers !! Core !! Spare Cores !! SAPs !! Memory !! Frequency !! Max PCIe<br>fanout | ! Feature<br>Code !! Feature<br>Name !! CPC Drawers !! Core !! Spare Cores !! SAPs !! Memory !! Frequency !! Max PCIe<br>fanout | ||
|- | |- | ||
− | | 0655 || Max34 || 1 || 34 || 2 || 4 || 512 | + | | 0655 || Max34 || 1 || 34 || 2 || 4 || 512 - 7.75 TiB || 5.2 GHz || 12 |
|- | |- | ||
− | | 0656 || Max71 || 2 || 71 || 2 || 8 || 512 | + | | 0656 || Max71 || 2 || 71 || 2 || 8 || 512 - 23.75 TiB || 5.2 GHz || 24 |
|- | |- | ||
− | | 0657 || Max108 || 3 || 108 || 2 || 12 || 512 | + | | 0657 || Max108 || 3 || 108 || 2 || 12 || 512 - 24320 TiB || 5.2 GHz || 36 |
|- | |- | ||
− | | 0658 || Max145 || 4 || 145 || 2 || 16 || 512 | + | | 0658 || Max145 || 4 || 145 || 2 || 16 || 512 - 31.75 TiB || 5.2 GHz || 48 |
|- | |- | ||
| 0659 || Max190 || 5 || 190 || 2 || 22 || 512 GiB - 39.75 TiB || 5.2 GHz || 60 | | 0659 || Max190 || 5 || 190 || 2 || 22 || 512 GiB - 39.75 TiB || 5.2 GHz || 60 | ||
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=== Drawer === | === Drawer === | ||
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{{empty section}} | {{empty section}} | ||
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** 17 metal layers | ** 17 metal layers | ||
* 9,200,000,000 transistors | * 9,200,000,000 transistors | ||
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* 5.2 GHz | * 5.2 GHz | ||
* 12 cores | * 12 cores | ||
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* [[14 nm process|14HP FinFET on SOI]] | * [[14 nm process|14HP FinFET on SOI]] | ||
** 17 metal layers | ** 17 metal layers | ||
− | * | + | * 9,700,000,000 billion transistors (''note that this number, from the technical document, is likely incorrect as it's the same number as the z14'') |
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* 960 MiB shared [[eDRAM]] [[L4 cache]]. | * 960 MiB shared [[eDRAM]] [[L4 cache]]. | ||
* Die size | * Die size |
Facts about "z15 - Microarchitectures - IBM"
codename | z15 + |
core count | 12 +, 9 +, 10 + and 11 + |
designer | IBM + |
first launched | September 12, 2019 + |
full page name | ibm/microarchitectures/z15 + |
instance of | microarchitecture + |
instruction set architecture | z/Architecture + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | z15 + |
pipeline stages | 17 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |