Semiconductor & Computer Engineering
From WikiChip
Editing ibm/microarchitectures/z15
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
| Latest revision | Your text | ||
| Line 7: | Line 7: | ||
|introduction=September 12, 2019 | |introduction=September 12, 2019 | ||
|process=14 nm | |process=14 nm | ||
| − | |cores | + | |cores=12 |
| − | |||
| − | |||
| − | |||
|type=Superscalar | |type=Superscalar | ||
|type 2=Pipelined | |type 2=Pipelined | ||
| Line 16: | Line 13: | ||
|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
| − | |||
| − | |||
|isa=z/Architecture | |isa=z/Architecture | ||
|l1i=128 KiB | |l1i=128 KiB | ||
| Line 166: | Line 161: | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
| − | ! colspan=" | + | ! colspan="6" | z15 T01 Configurations |
|- | |- | ||
| − | ! Feature<br>Code !! Feature<br>Name !! CPC Drawers | + | ! Feature<br>Code !! Feature<br>Name !! CPC Drawers || Core || Spare Cores || SAPs |
|- | |- | ||
| − | | 0655 || Max34 || 1 || 34 || 2 || 4 | + | | 0655 || Max34 || 1 || 34 || 2 || 4 |
|- | |- | ||
| − | | 0656 || Max71 || 2 || 71 || 2 || 8 | + | | 0656 || Max71 || 2 || 71 || 2 || 8 |
|- | |- | ||
| − | | 0657 || Max108 || 3 || 108 || 2 || 12 | + | | 0657 || Max108 || 3 || 108 || 2 || 12 |
|- | |- | ||
| − | | 0658 || Max145 || 4 || 145 || 2 || 16 | + | | 0658 || Max145 || 4 || 145 || 2 || 16 |
|- | |- | ||
| − | | 0659 || Max190 || 5 || 190 || 2 || 22 | + | | 0659 || Max190 || 5 || 190 || 2 || 22 |
|} | |} | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
== System == | == System == | ||
| Line 192: | Line 180: | ||
=== Drawer === | === Drawer === | ||
| − | |||
| − | |||
| − | |||
{{empty section}} | {{empty section}} | ||
| Line 207: | Line 192: | ||
** 17 metal layers | ** 17 metal layers | ||
* 9,200,000,000 transistors | * 9,200,000,000 transistors | ||
| − | |||
| − | |||
* 5.2 GHz | * 5.2 GHz | ||
* 12 cores | * 12 cores | ||
| Line 225: | Line 208: | ||
* [[14 nm process|14HP FinFET on SOI]] | * [[14 nm process|14HP FinFET on SOI]] | ||
** 17 metal layers | ** 17 metal layers | ||
| − | * | + | * 9,700,000,000 billion transistors (''note that this number, from the technical document, is likely incorrect as it's the same number as the z14'') |
| − | |||
| − | |||
* 960 MiB shared [[eDRAM]] [[L4 cache]]. | * 960 MiB shared [[eDRAM]] [[L4 cache]]. | ||
* Die size | * Die size | ||
Facts about "z15 - Microarchitectures - IBM"
| codename | z15 + |
| core count | 12 +, 9 +, 10 + and 11 + |
| designer | IBM + |
| first launched | September 12, 2019 + |
| full page name | ibm/microarchitectures/z15 + |
| instance of | microarchitecture + |
| instruction set architecture | z/Architecture + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | z15 + |
| pipeline stages | 17 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
