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|l1i=32 KiB | |l1i=32 KiB | ||
|l1i per=core | |l1i per=core | ||
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|l1d=32 KiB | |l1d=32 KiB | ||
|l1d per=core | |l1d per=core | ||
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|l2=512 KiB | |l2=512 KiB | ||
− | |l2 per=core | + | |l2 per=core |
− | + | |l3=120 MiB | |
− | |l3= | + | |l3 per=chip |
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|predecessor=POWER8+ | |predecessor=POWER8+ | ||
|predecessor link=ibm/microarchitectures/power8+ | |predecessor link=ibm/microarchitectures/power8+ | ||
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== Code names == | == Code names == | ||
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|- | |- | ||
− | | | + | ! Codename || Description |
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− | | {{ibm| | + | | {{ibm|Sforza|l=core}} || General-purpose scale-out processors |
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− | + | | {{ibm|Monza|l=core}} || | |
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− | | | + | | {{ibm|LaGrange|l=core}} || |
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* 17-layer metal stack | * 17-layer metal stack | ||
* 8,000,000,000 transistors | * 8,000,000,000 transistors | ||
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* 693.37 mm² die size | * 693.37 mm² die size | ||
* 25.228 mm x 27.48416 mm | * 25.228 mm x 27.48416 mm | ||
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* 17-layer metal stack | * 17-layer metal stack | ||
* 8,000,000,000 transistors | * 8,000,000,000 transistors | ||
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* 693.37 mm² die size | * 693.37 mm² die size | ||
* 25.228 mm x 27.48416 mm | * 25.228 mm x 27.48416 mm | ||
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== Bibliography == | == Bibliography == | ||
− | * {{ | + | * {{hcbib|28}} |
− | * {{ | + | * {{hcbib|30}} |
== See also == | == See also == |
Facts about "POWER9 - Microarchitectures - IBM"
codename | POWER9 + |
core count | 24 +, 4 +, 8 +, 12 +, 16 + and 20 + |
designer | IBM + |
first launched | August 2017 + |
full page name | ibm/microarchitectures/power9 + |
instance of | microarchitecture + |
instruction set architecture | Power ISA v3.0B + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | POWER9 + |
phase-out | 2020 + |
pipeline stages (max) | 16 + |
pipeline stages (min) | 12 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |