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Because the [[MACs]] are not [[pipelined]], they set the clock cycle. At 800 MHz, the chip is capable of 4,096 [[FLOPs]]/cycle (2*16*16*8) or 3.28 TeraFLOPS of raw compute power. | Because the [[MACs]] are not [[pipelined]], they set the clock cycle. At 800 MHz, the chip is capable of 4,096 [[FLOPs]]/cycle (2*16*16*8) or 3.28 TeraFLOPS of raw compute power. | ||
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== Die == | == Die == |
Facts about "Pixel Visual Core (PVC) - Google"
base frequency | 800 MHz (0.8 GHz, 800,000 kHz) + |
designer | Google + |
first announced | October 17, 2017 + |
first launched | October 17, 2017 + |
full page name | google/pixel visual core + |
isa | vISA + and pISA + |
ldate | October 17, 2017 + |
manufacturer | TSMC + |
market segment | Mobile + and Embedded + |
name | Pixel Visual Core + |
part number | X726C502 + |
process | 28 nm (0.028 μm, 2.8e-5 mm) + |
s-spec | SR3HX + |
tdp | 8 W (8,000 mW, 0.0107 hp, 0.008 kW) + |
technology | CMOS + |