Semiconductor & Computer Engineering
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Difference between revisions of "exponential technology/x704/500"
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Revision as of 23:02, 23 June 2017
Template:mpu X704 500 MHz was a PowerPC-compatible microprocessor operating at 500 MHz announced in January 1997 by Exponential Technology. The company folded before the model ever reaching market (See X704 § History).
Cache
- Main article: X704 § Cache
Level 3 can be provided externally with cache size of 512 KiB to 2 MiB.
| Cache Info [Edit Values] | ||
| L1I$ | 2 KiB 2,048 B 0.00195 MiB |
1x2 KiB direct mapped |
| L1D$ | 2 KiB 2,048 B 0.00195 MiB |
1x2 KiB direct mapped |
| L2$ | 32 KiB 0.0313 MiB 32,768 B 3.051758e-5 GiB |
1x32 KiB 8-way set associative |
Graphics
This SoC has no integrated graphics processing unit.
Features
- Fully PowerPC 60x-compatible architecture
- IEEE 1149.1-compliant JTAG test access port
- IEEE 754-compliant single-precision and double-precision arithmetic
- Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
- Support for all PowerPC cache operations
- Support for PowerEndian and BigEndian modes
Documents
Manuals
- X704 Technical Summary, 1996
See also
Facts about "X704-500 - Exponential Technology"
| l1d$ description | direct mapped + |
| l1d$ size | 2 KiB (2,048 B, 0.00195 MiB) + |
| l1i$ description | direct mapped + |
| l1i$ size | 2 KiB (2,048 B, 0.00195 MiB) + |
| l2$ description | 8-way set associative + |
| l2$ size | 0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) + |
