Editing exponential technology/x704/500

{{expotech title|X704-500}}
{{chip
| name                = X704-500
| no image            = Yes
| image               = 
| image size          = 
| caption             = 
| designer            = Exponential Technology
| manufacturer        = Hitachi
| model number        = X704-500
| part number         = 
| market              = Desktop
| first announced     = January 7, 1997
| first launched      = 
| last order          = 
| last shipment       = 

| family              = X704
| series              = 
| locked              = 
| frequency           = 500 MHz
| bus type            = 60x bus
| bus speed           = 100 MHz
| bus rate            = 
| clock multiplier    = 5

| microarch           = X704
| platform            = CHRP
| chipset             = 
| core name           = 
| core family         = 
| core model          = 
| core stepping       = 
| process             = 500 nm
| transistors         = 2,700,000
| technology          = BiCMOS
| die size            = 150 mm²
| word size           = 32 bit
| core count          = 1
| thread count        = 1
| max cpus            = 1
| max memory          = 
| max memory addr     = 


| power               = 85 W
| v core              = 3.6 V
| v core tolerance    = 
| sdp                 = 
| tdp                 = 
| ctdp down           = 
| ctdp down frequency = 
| ctdp up             = 
| ctdp up frequency   = 
| temp min            = 
| temp max            = 
| tjunc min           = 
| tjunc max           = 
| tcase min           = 
| tcase max           = 
| tstorage min        = 
| tstorage max        = 

| packaging           = Yes
| package 0           = CBGA-359
| package 0 type      = CBGA
| package 0 pins      = 359
| package 0 pitch     = 1.27 mm
| package 0 width     = 25.4 mm
| package 0 length    = 25.4 mm
| package 0 height    = 2.2 mm
| socket 0            = BGA-359
| socket 0 type       = BGA
}}
'''X704 500 MHz''' was a [[PowerPC]]-compatible microprocessor operating at 500 MHz announced in January [[1997]] by [[Exponential Technology]]. The company folded before the model ever reaching market (See [[exponential_technology/x704#History|X704 § History]]).

== Cache ==
{{main|exponential_technology/microarchitectures/x704#Memory_Hierarchy|l1=X704 § Cache}}
Level 3 can be provided externally with cache size of 512 KB to 2 MB.
{{cache info
|l1i cache=2 KB
|l1i break=1x2 KB
|l1i desc=direct mapped
|l1i extra=
|l1d cache=2 KB
|l1d break=1x2 KB
|l1d desc=direct mapped
|l1d extra=
|l2 cache=32 KB
|l2 break=1x32 KB
|l2 desc=8-way set associative
|l2 extra=
|l3 cache=
|l3 break=
|l3 desc=
|l3 extra=
}}

== Graphics ==
This SoC has no integrated graphics processing unit.

== Features ==
* Fully PowerPC 60x-compatible architecture
* IEEE 1149.1-compliant JTAG test access port
* IEEE 754-compliant single-precision and double-precision arithmetic
* Support for standard PowerPC 60X bus with 64 bits of data and 32 bits of address
* Support for all PowerPC cache operations
* Support for PowerEndian and BigEndian modes

== Documents ==

=== Manuals ===
* [[:File:X704 technical summary.pdf|X704 Technical Summary]], 1996

== See also ==
* [[PowerPC]]
* {{expotech|X704}}
base frequency	500 MHz (0.5 GHz, 500,000 kHz) +
bus speed	100 MHz (0.1 GHz, 100,000 kHz) +
bus type	60x bus +
clock multiplier	5 +
core count	1 +
core voltage	3.6 V (36 dV, 360 cV, 3,600 mV) +
designer	Exponential Technology +
die area	150 mm² (0.233 in², 1.5 cm², 150,000,000 µm²) +
family	X704 +
first announced	January 7, 1997 +
full page name	exponential technology/x704/500 +
instance of	microprocessor +
l1d$ description	direct mapped +
l1d$ size	2 KiB (2,048 B, 0.00195 MiB) +
l1i$ description	direct mapped +
l1i$ size	2 KiB (2,048 B, 0.00195 MiB) +
l2$ description	8-way set associative +
l2$ size	0.0313 MiB (32 KiB, 32,768 B, 3.051758e-5 GiB) +
ldate	January 7, 1997 +
manufacturer	Hitachi +
market segment	Desktop +
max cpu count	1 +
microarchitecture	X704 +
model number	X704-500 +
name	X704-500 +
platform	CHRP +
power dissipation	85 W (85,000 mW, 0.114 hp, 0.085 kW) +
process	500 nm (0.5 μm, 5.0e-4 mm) +
smp max ways	1 +
technology	BiCMOS +
thread count	1 +
transistor count	2,700,000 +
word size	32 bit (4 octets, 8 nibbles) +