From WikiChip
Editing cavium/octeon plus
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 37: | Line 37: | ||
== Members == | == Members == | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
=== CN57xx Series === | === CN57xx Series === | ||
The CN57xx series come with [[6 cores|6]] to [[12 cores|12]] {{cavium|cnMIPS|l=arch}} cores. CN57xx series is designed for storage devices, incorporating hardware support for [[RAID]] 5 and 6. All models incorporate the following features: | The CN57xx series come with [[6 cores|6]] to [[12 cores|12]] {{cavium|cnMIPS|l=arch}} cores. CN57xx series is designed for storage devices, incorporating hardware support for [[RAID]] 5 and 6. All models incorporate the following features: |
Facts about "OCTEON Plus - Cavium"
designer | Cavium + |
first announced | October 9, 2006 + |
first launched | February 2007 + |
full page name | cavium/octeon plus + |
instance of | system on a chip family + |
instruction set architecture | MIPS64 + |
main designer | Cavium + |
manufacturer | TSMC + |
microarchitecture | cnMIPS + |
name | Cavium OCTEON Plus + |
package | FCBGA-1521 + |
process | 90 nm (0.09 μm, 9.0e-5 mm) + |
socket | BGA-1521 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |