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| | microarch = cnMIPS | | | microarch = cnMIPS |
| | word = 64 bit | | | word = 64 bit |
− | | proc = 90 nm | + | | proc = 130 nm |
| | tech = CMOS | | | tech = CMOS |
| | clock min = 600 MHz | | | clock min = 600 MHz |
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| }} | | }} |
| '''OCTEON Plus''' was a family of {{arch|64}} [[multi-core]] [[MIPS]] microprocessors designed by [[Cavium]] and introduced in [[2007]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the {{\\|OCTEON}} family offering double the cache, double the clock speeds, and double the number of various acceleration units. | | '''OCTEON Plus''' was a family of {{arch|64}} [[multi-core]] [[MIPS]] microprocessors designed by [[Cavium]] and introduced in [[2007]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the {{\\|OCTEON}} family offering double the cache, double the clock speeds, and double the number of various acceleration units. |
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− | == Overview ==
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− | The OCTEON Plus family was announced in late [[2006]] as a successor to the original {{\\|OCTEON}} family. As with the previous family, the OCTEON Plus is also based on the {{cavium|cnMIPS|l=arch}} microarchitecture. These new processors operate at twice the previous clock speeds and introduced a number of incremental improvements such as a larger cache.
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− | == Members ==
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− | === CN50xx Series ===
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− | {{empty section}}
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− | === CN52xx Series ===
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− | {{empty section}}
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− | === CN54xx Series ===
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− | {{empty section}}
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− | === CN55xx Series ===
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− | {{empty section}}
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− | === CN56xx Series ===
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− | {{empty section}}
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− | === CN57xx Series ===
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− | The CN57xx series come with [[6 cores|6]] to [[12 cores|12]] {{cavium|cnMIPS|l=arch}} cores. CN57xx series is designed for storage devices, incorporating hardware support for [[RAID]] 5 and 6. All models incorporate the following features:
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− | * PCI Express x4, x8
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− | * 2x (4x SGMII or 1x XAUI)
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− | * 72/144 bit DD2-800 memory
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− | <!-- NOTE:
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− | This table is generated automatically from the data in the actual articles.
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− | If a microprocessor is missing from the list, an appropriate article for it needs to be
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− | created and tagged accordingly.
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− |
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− | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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− | -->
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− | <div style="overflow-x: auto;">
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− | <table class="wikitable sortable tc4 tc10 tc11 tc12 tc13 tc14 tc15" style="min-width: 1200px;">
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− | <tr><th colspan="14" style="background:#D6D6FF;">CN57xx-Series Microprocessors</th></tr>
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− | <tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="4">[[Hardware Accelerators]]</th></tr>
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− | <tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th><th>Encryption</th><th>Compression</th><th>TCP</th><th>QoS</th></tr>
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− | {{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN57xx]]
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− | |?full page name
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− | |?model number
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− | |?release price
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− | |?first launched
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− | |?core count
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− | |?l2$ size#MiB
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− | |?power dissipation
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− | |?base frequency
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− | |?supported memory type
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− | |?max memory
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− | |?has ecc memory support
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− | |?has hardware accelerators for cryptography
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− | |?has hardware accelerators for data compression
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− | |?has hardware accelerators for tcp packet processing
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− | |?has hardware accelerators for network quality of service processing
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− | |format=template
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− | |template=proc table 3
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− | |userparam=15:11
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− | |mainlabel=-
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− | |sort=model number
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− | }}
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− | {{table count|col=14|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN57xx]]}}
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− | </table>
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− | </div>
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− |
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− | === CN58xx Series ===
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− | The CN58xx series come with [[4 cores|4]] to [[16 cores|16]] {{cavium|cnMIPS|l=arch}} cores. All models incorporate the following features:
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− | * Pin compatible with {{\\|Octeon|Octeon CN38xx Series}}.
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− | * Network interfaces support for up to 2x [[RGMII]] or 2x [[SPI-4.2]]
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− | * 72/144 bit DD2-800 memory
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− | * 2x 18bit RLDRAM II controllers
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− | * 64-bit 133 MHz [[PCI-X]]
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− | <!-- NOTE:
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− | This table is generated automatically from the data in the actual articles.
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− | If a microprocessor is missing from the list, an appropriate article for it needs to be
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− | created and tagged accordingly.
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− |
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− | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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− | -->
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− | <div style="overflow-x: auto;">
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− | <table class="wikitable sortable tc4 tc10 tc11 tc12 tc13 tc14 tc15" style="min-width: 1350px;">
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− | <tr><th colspan="15" style="background:#D6D6FF;">CN58xx-Series Microprocessors</th></tr>
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− | <tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="5">[[Hardware Accelerators]]</th></tr>
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− | <tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th><th>Encryption</th><th>Compression</th><th>RegEx</th><th>TCP</th><th>QoS</th></tr>
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− | {{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN58xx]]
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− | |?full page name
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− | |?model number
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− | |?release price
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− | |?first launched
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− | |?core count
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− | |?l2$ size#MiB
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− | |?power dissipation
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− | |?base frequency
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− | |?supported memory type
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− | |?max memory
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− | |?has ecc memory support
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− | |?has hardware accelerators for cryptography
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− | |?has hardware accelerators for data compression
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− | |?has hardware accelerators for regular expression
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− | |?has hardware accelerators for tcp packet processing
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− | |?has hardware accelerators for network quality of service processing
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− | |format=template
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− | |template=proc table 3
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− | |userparam=16:11
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− | |mainlabel=-
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− | |sort=model number
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− | }}
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− | {{table count|col=15|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN58xx]]}}
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− | </table>
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− | </div>
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− |
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− | == Datasheet ==
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− | * [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]]
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