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Latest revision Your text
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| microarch        = cnMIPS
 
| microarch        = cnMIPS
 
| word              = 64 bit
 
| word              = 64 bit
| proc              = 90 nm
+
| proc              = 130 nm
 
| tech              = CMOS
 
| tech              = CMOS
 
| clock min        = 600 MHz
 
| clock min        = 600 MHz
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}}
 
}}
 
'''OCTEON Plus''' was a family of {{arch|64}} [[multi-core]] [[MIPS]] microprocessors designed by [[Cavium]] and introduced in [[2007]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the {{\\|OCTEON}} family offering double the cache, double the clock speeds, and double the number of various acceleration units.
 
'''OCTEON Plus''' was a family of {{arch|64}} [[multi-core]] [[MIPS]] microprocessors designed by [[Cavium]] and introduced in [[2007]]. These processors are primarily marketed towards makers of network infrastructure, enterprise and data center devices. The OCTEON Plus family is a successor to the {{\\|OCTEON}} family offering double the cache, double the clock speeds, and double the number of various acceleration units.
 
== Overview ==
 
The OCTEON Plus family was announced in late [[2006]] as a successor to the original {{\\|OCTEON}} family. As with the previous family, the OCTEON Plus is also based on the {{cavium|cnMIPS|l=arch}} microarchitecture. These new processors operate at twice the previous clock speeds and introduced a number of incremental improvements such as a larger cache.
 
 
== Members ==
 
=== CN50xx Series ===
 
{{empty section}}
 
=== CN52xx Series ===
 
{{empty section}}
 
=== CN54xx Series ===
 
{{empty section}}
 
=== CN55xx Series ===
 
{{empty section}}
 
=== CN56xx Series ===
 
{{empty section}}
 
=== CN57xx Series ===
 
The CN57xx series come with [[6 cores|6]] to [[12 cores|12]] {{cavium|cnMIPS|l=arch}} cores. CN57xx series is designed for storage devices, incorporating hardware support for [[RAID]] 5 and 6. All models incorporate the following features:
 
 
* PCI Express x4, x8
 
* 2x (4x SGMII or 1x XAUI)
 
* 72/144 bit DD2-800 memory
 
<!-- NOTE:
 
          This table is generated automatically from the data in the actual articles.
 
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
          created and tagged accordingly.
 
 
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
-->
 
<div style="overflow-x: auto;">
 
<table class="wikitable sortable tc4 tc10 tc11 tc12 tc13 tc14 tc15" style="min-width: 1200px;">
 
<tr><th colspan="14" style="background:#D6D6FF;">CN57xx-Series Microprocessors</th></tr>
 
<tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="4">[[Hardware Accelerators]]</th></tr>
 
<tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th><th>Encryption</th><th>Compression</th><th>TCP</th><th>QoS</th></tr>
 
{{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN57xx]]
 
|?full page name
 
|?model number
 
|?release price
 
|?first launched
 
|?core count
 
|?l2$ size#MiB
 
|?power dissipation
 
|?base frequency
 
|?supported memory type
 
|?max memory
 
|?has ecc memory support
 
|?has hardware accelerators for cryptography
 
|?has hardware accelerators for data compression
 
|?has hardware accelerators for tcp packet processing
 
|?has hardware accelerators for network quality of service processing
 
|format=template
 
|template=proc table 3
 
|userparam=15:11
 
|mainlabel=-
 
|sort=model number
 
}}
 
{{table count|col=14|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN57xx]]}}
 
</table>
 
</div>
 
 
=== CN58xx Series ===
 
The CN58xx series come with [[4 cores|4]] to [[16 cores|16]] {{cavium|cnMIPS|l=arch}} cores. All models incorporate the following features:
 
 
* Pin compatible with {{\\|Octeon|Octeon CN38xx Series}}.
 
* Network interfaces support for up to 2x [[RGMII]] or 2x [[SPI-4.2]]
 
* 72/144 bit DD2-800 memory
 
* 2x 18bit RLDRAM II controllers
 
* 64-bit 133 MHz [[PCI-X]]
 
<!-- NOTE:
 
          This table is generated automatically from the data in the actual articles.
 
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
          created and tagged accordingly.
 
 
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
-->
 
<div style="overflow-x: auto;">
 
<table class="wikitable sortable tc4 tc10 tc11 tc12 tc13 tc14 tc15" style="min-width: 1350px;">
 
<tr><th colspan="15" style="background:#D6D6FF;">CN58xx-Series Microprocessors</th></tr>
 
<tr><th colspan="7">CPU</th><th colspan="3">Memory</th><th colspan="5">[[Hardware Accelerators]]</th></tr>
 
<tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th><th>Encryption</th><th>Compression</th><th>RegEx</th><th>TCP</th><th>QoS</th></tr>
 
{{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN58xx]]
 
|?full page name
 
|?model number
 
|?release price
 
|?first launched
 
|?core count
 
|?l2$ size#MiB
 
|?power dissipation
 
|?base frequency
 
|?supported memory type
 
|?max memory
 
|?has ecc memory support
 
|?has hardware accelerators for cryptography
 
|?has hardware accelerators for data compression
 
|?has hardware accelerators for regular expression
 
|?has hardware accelerators for tcp packet processing
 
|?has hardware accelerators for network quality of service processing
 
|format=template
 
|template=proc table 3
 
|userparam=16:11
 
|mainlabel=-
 
|sort=model number
 
}}
 
{{table count|col=15|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON Plus]][[microprocessor series::CN58xx]]}}
 
</table>
 
</div>
 
 
== Datasheet ==
 
* [[:File:octeon plus cn58xx (rev 1.4).pdf|OCTEON CN58XX Processors Product Brief]]
 

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Facts about "OCTEON Plus - Cavium"
designerCavium +
first announcedOctober 9, 2006 +
first launchedFebruary 2007 +
full page namecavium/octeon plus +
instance ofsystem on a chip family +
instruction set architectureMIPS64 +
main designerCavium +
manufacturerTSMC +
microarchitecturecnMIPS +
nameCavium OCTEON Plus +
packageFCBGA-1521 +
process90 nm (0.09 μm, 9.0e-5 mm) +
socketBGA-1521 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +