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Editing cavium/octeon/cn3860-500bg1521-scp (section)

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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3860-500 SCP - Cavium#package +
base frequency500 MHz (0.5 GHz, 500,000 kHz) +
core count16 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedSeptember 13, 2004 +
first launchedJune 1, 2005 +
full page namecavium/octeon/cn3860-500bg1521-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size0.625 MiB (640 KiB, 655,360 B, 6.103516e-4 GiB) +
l1d$ description64-way set associative +
l1d$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
l1i$ description64-way set associative +
l1i$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateJune 1, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (20.741 GB/s, 12,206.08 MiB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3860-500 SCP +
nameCavium CN3860-500 SCP +
packageFCBGA-1521 +
part numberCN3860-500BG1521-SCP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count16 +
word size64 bit (8 octets, 16 nibbles) +