Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "cavium/octeon/cn3840-400bg1521-exp"
| Line 89: | Line 89: | ||
| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
| − | The '''CN3840-400 EXP''' is a {{arch|64}} [[octa-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates | + | The '''CN3840-400 EXP''' is a {{arch|64}} [[octa-core]] [[MIPS]] communication [[microprocessor]] designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates eight {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory. |
Revision as of 20:44, 10 December 2016
Template:mpu The CN3840-400 EXP is a 64-bit octa-core MIPS communication microprocessor designed by Cavium and introduced in 2005. This processor, which incorporates eight cnMIPS cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
