From WikiChip
Editing cavium/octeon/cn3830-400bg1521-nsp

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 1: Line 1:
 
{{cavium title|CN3830-400 NSP}}
 
{{cavium title|CN3830-400 NSP}}
{{chip
+
{{mpu
 
| name                = Cavium CN3830-400 NSP
 
| name                = Cavium CN3830-400 NSP
 
| no image            =  
 
| no image            =  
Line 10: Line 10:
 
| model number        = CN3830-400 NSP
 
| model number        = CN3830-400 NSP
 
| part number        = CN3830-400BG1521-NSP
 
| part number        = CN3830-400BG1521-NSP
 +
| part number 1      =
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
| part number 4      =
 
 
| market              = Networking
 
| market              = Networking
 
| first announced    = September 13, 2004  
 
| first announced    = September 13, 2004  
Line 78: Line 78:
 
| tambient max        =  
 
| tambient max        =  
  
|package module 1={{packages/cavium/fcbga-1521}}
+
| packaging          = Yes
 +
| package 0          = BGA-1521
 +
| package 0 type      = BGA
 +
| package 0 pins      = 1521
 +
| package 0 pitch    =
 +
| package 0 width    =
 +
| package 0 length    =
 +
| package 0 height    =
 +
| socket 0            =
 +
| socket 0 type      =
 
}}
 
}}
The '''CN3830-400 NSP''' is a {{arch|64}} [[quad-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates four {{cavium|cnMIPS|l=arch}} cores, operates at 400 MHz. This processor includes a number of hardware networking accelerators including units for high-performance packet I/O processing, QoS, TCP, encryption, and RegEx. This MPU supports up to 16 GiB of DDR2-800 ECC memory.
 
 
== Cache ==
 
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
 
{{cache size
 
|l1 cache=160 KiB
 
|l1i cache=128 KiB
 
|l1i break=4x32 KiB
 
|l1i desc=64-way set associative
 
|l1d cache=32 KiB
 
|l1d break=4x8 KiB
 
|l1d desc=64-way set associative
 
|l1d policy=Write-through
 
|l2 cache=1 MiB
 
|l2 break=1x1 MiB
 
|l2 desc=8-way set associative
 
}}
 
 
== Memory controller ==
 
{{memory controller
 
|type=DDR2-800
 
|ecc=Yes
 
|max mem=16 GiB
 
|controllers=1
 
|channels=1
 
|width=128 bit
 
|max bandwidth=11.92 GiB/s
 
|bandwidth schan=11.92 GiB/s
 
}}
 
 
== Expansions ==
 
{{expansions
 
|pcix width=64 bit
 
|pcix clock=133.33 MHz
 
|pcix rate=1,017.25 MiB/s
 
|pcix extra=host or slave
 
|uart=yes
 
|uart ports=2
 
|gp io=Yes
 
}}
 
 
== Networking ==
 
{{network
 
|mii opts=Yes
 
|rgmii=yes
 
|rgmii ports=8
 
|spi opts=Yes
 
|spi42=Yes
 
|spi42 ports=2
 
}}
 
 
== Hardware Accelerators ==
 
{{accelerators
 
|encryption=Yes
 
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
 
|regex=Yes
 
|regex feature=16 Engines
 
|compression=Yes
 
|decompression=Yes
 
|tcp=Yes
 
|qos=Yes
 
}}
 
 
== Block diagram ==
 
[[File:octeon cn38xx block diagram.png|750px]]
 
 
== Datasheet ==
 
* [[:File:octeon cn38xx and cn36xx product brief.pdf|OCTEON CN38XX/CN36XX 4 to 16-Core Product Brief]]
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3830-400 NSP - Cavium#package +
base frequency400 MHz (0.4 GHz, 400,000 kHz) +
core count4 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedSeptember 13, 2004 +
first launchedJune 1, 2005 +
full page namecavium/octeon/cn3830-400bg1521-nsp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size160 KiB (163,840 B, 0.156 MiB) +
l1d$ description64-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description64-way set associative +
l1i$ size128 KiB (131,072 B, 0.125 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +
ldateJune 1, 2005 +
main imageFile:octeon cn38xx.png +
manufacturerTSMC +
market segmentNetworking +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth11.92 GiB/s (12,206.08 MiB/s, 12.799 GB/s, 12,799.003 MB/s, 0.0116 TiB/s, 0.0128 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3830-400 NSP +
nameCavium CN3830-400 NSP +
packageFCBGA-1521 +
part numberCN3830-400BG1521-NSP +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3800 +
smp max ways1 +
supported memory typeDDR2-800 +
technologyCMOS +
thread count4 +
word size64 bit (8 octets, 16 nibbles) +