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{{cavium title|CN3120-550 NSP}}
 
{{cavium title|CN3120-550 NSP}}
{{chip
+
{{mpu
 
| name                = Cavium CN3120-550 NSP
 
| name                = Cavium CN3120-550 NSP
 
| no image            =  
 
| no image            =  
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| designer            = Cavium
 
| designer            = Cavium
 
| manufacturer        = TSMC
 
| manufacturer        = TSMC
| model number        = CN3120-550 NSP
+
| model number        = CN3120
 
| part number        = CN3120-550BG868-NSP
 
| part number        = CN3120-550BG868-NSP
 +
| part number 1      =
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
| part number 4      =
 
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = January 30, 2006  
 
| first announced    = January 30, 2006  
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| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
| release price      = $125.00
+
| release price      =  
  
 
| family              = OCTEON
 
| family              = OCTEON
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| max memory addr    =  
 
| max memory addr    =  
  
 
+
| electrical          =
| power              = 7 W
+
| power              =  
 
| v core              =  
 
| v core              =  
 
| v core tolerance    =  
 
| v core tolerance    =  
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| tambient max        =  
 
| tambient max        =  
  
|package module 1={{packages/cavium/hsbga-868}}
+
| packaging          = Yes
}}
+
| package 0          = BGA-868
The '''CN3120-550 NSP''' is a {{arch|64}} [[dual-core]] [[MIPS]] network service [[microprocessor]] (NSP) designed by [[Cavium]] and introduced in [[2006]]. This processor, which incorporates a two {{cavium|cnMIPS|l=arch}} cores, operates at 555 MHz and dissipates 7 Watts. This processor includes a number of hardware accelerators for network services such as [[encryption]], [[compression]] & decompression, [[RegEx]] engine, [[TCP]], and [[QoS]]. This MPU supports up to 4 GiB of 64-bit DDR2-667 ECC memory.
+
| package 0 type     = BGA
 
+
| package 0 pins      = 868
== Cache ==
+
| package 0 pitch    =  
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
+
| package 0 width     =  
{{cache size
+
| package 0 length    =  
|l1 cache=80 KiB
+
| package 0 height    =  
|l1i cache=64 KiB
+
| socket 0            =  
|l1i break=2x32 KiB
+
| socket 0 type       =  
|l1i desc=4-way set associative
 
|l1d cache=16 KiB
 
|l1d break=2x8 KiB
 
|l1d desc=64-way set associative
 
|l1d policy=Write-through
 
|l2 cache=256 KiB
 
|l2 break=1x256 KiB
 
|l2 desc=8-way set associative
 
}}
 
 
 
== Memory controller ==
 
{{memory controller
 
|type=DDR2-667
 
|ecc=Yes
 
|max mem=4 GiB
 
|controllers=1
 
|channels=1
 
|width=64 bit
 
|max bandwidth=4.97 GiB/s
 
|bandwidth schan=4.97 GiB/s
 
}}
 
 
 
Optional low-latency controller for content-based processing and meta data
 
 
 
{{memory controller
 
|type=DDR2-667
 
|ecc=Yes
 
|max mem=2 GiB
 
|controllers=1
 
|channels=1
 
|width=16 bit
 
|max bandwidth=1.24 GiB/s
 
|bandwidth schan=1.24 GiB/s
 
}}
 
 
 
== Expansions ==
 
{{expansions
 
|pcix width=32 bit
 
|pcix clock=100 MHz
 
|pcix rate=381.5 MiB/s
 
|pci extra=host or slave
 
|usb revision=2.0
 
|usb ports=1
 
|usb rate=60 MB/s
 
|usb extra=host / PHY
 
|uart=yes
 
|uart ports=2
 
|gp io=Yes
 
}}
 
 
 
== Networking ==
 
{{network
 
|mii opts=Yes
 
|rgmii=yes
 
|rgmii ports=3
 
|gmii=yes
 
|gmii ports=1
 
|pcm=Yes
 
}}
 
 
 
== Hardware Accelerators ==
 
{{accelerators
 
|encryption=Yes
 
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
 
|regex=Yes
 
|regex feature=8 Engines
 
|compression=Yes
 
|decompression=Yes
 
|tcp=Yes
 
|qos=Yes
 
 
}}
 
}}
 
== Block diagram ==
 
[[File:octeon cn31xx block diagram.png|750px]]
 
 
== Datasheet ==
 
* [[:File:octeon cn31xx product brief.pdf|OCTEON CN31XX Single- and Dual-Core Product Brief]]
 

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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
CN3120-550 NSP - Cavium#package +
base frequency550 MHz (0.55 GHz, 550,000 kHz) +
core count2 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3120-550bg868-nsp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for data compressiontrue +
has hardware accelerators for data decompressiontrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for regular expressiontrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size80 KiB (81,920 B, 0.0781 MiB) +
l1d$ description64-way set associative +
l1d$ size16 KiB (16,384 B, 0.0156 MiB) +
l1i$ description4-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description8-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:octeon cn31xx.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory4,096 MiB (4,194,304 KiB, 4,294,967,296 B, 4 GiB, 0.00391 TiB) +
max memory bandwidth4.97 GiB/s (5,089.28 MiB/s, 5.336 GB/s, 5,336.497 MB/s, 0.00485 TiB/s, 0.00534 TB/s) + and 1.24 GiB/s (1,269.76 MiB/s, 1.331 GB/s, 1,331.44 MB/s, 0.00121 TiB/s, 0.00133 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3120-550 NSP +
nameCavium CN3120-550 NSP +
packageHSBGA-868 +
part numberCN3120-550BG868-NSP +
power dissipation7 W (7,000 mW, 0.00939 hp, 0.007 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
release price$ 125.00 (€ 112.50, £ 101.25, ¥ 12,916.25) +
seriesCN3100 +
smp max ways1 +
supported memory typeDDR2-667 +
technologyCMOS +
thread count2 +
word size64 bit (8 octets, 16 nibbles) +