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{{cavium title|CN3010-400 SCP}}
 
{{cavium title|CN3010-400 SCP}}
{{chip
+
{{mpu
 
| name                = Cavium CN3010-400 SCP
 
| name                = Cavium CN3010-400 SCP
 
| no image            =  
 
| no image            =  
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| designer            = Cavium
 
| designer            = Cavium
 
| manufacturer        = TSMC
 
| manufacturer        = TSMC
| model number        = CN3010-400 SCP
+
| model number        = CN3010
 
| part number        = CN3010-400BG525-SCP
 
| part number        = CN3010-400BG525-SCP
 +
| part number 1      =
 
| part number 2      =  
 
| part number 2      =  
 
| part number 3      =  
 
| part number 3      =  
| part number 4      =
 
 
| market              = Embedded
 
| market              = Embedded
 
| first announced    = January 30, 2006  
 
| first announced    = January 30, 2006  
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| last order          =  
 
| last order          =  
 
| last shipment      =  
 
| last shipment      =  
| release price      =  
+
| release price      = $29
  
 
| family              = OCTEON
 
| family              = OCTEON
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| max memory addr    =  
 
| max memory addr    =  
  
 
+
| electrical          = Yes
 
| power              = 3 W
 
| power              = 3 W
 
| v core              =  
 
| v core              =  
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}}
 
}}
 
The '''CN3010-400 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-400bg350-scp|CN3005 equivalent}}, double DDR2 memory access, as well as support for TDM/PCM (VoIP support).
 
The '''CN3010-400 SCP''' is a {{arch|64}} [[single-core]] [[MIPS]] secure communication [[microprocessor]] (SCP) designed by [[Cavium]] and introduced in early [[2006]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 400 MHz and dissipates 3 Watts. This processors includes a number of hardware security communication accelerators including units for encryption, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. This model includes double as much cache as the {{\\|cn3005-400bg350-scp|CN3005 equivalent}}, double DDR2 memory access, as well as support for TDM/PCM (VoIP support).
 
== Cache ==
 
{{main|cavium/microarchitectures/cnmips#Memory_Hierarchy|l1=cnMIPS § Cache}}
 
{{cache size
 
|l1 cache=24 KiB
 
|l1i cache=16 KiB
 
|l1i break=1x16 KiB
 
|l1i desc=2-way set associative
 
|l1d cache=8 KiB
 
|l1d break=1x8 KiB
 
|l1d desc=64-way set associative
 
|l1d policy=Write-through
 
|l2 cache=128 KiB
 
|l2 break=1x128 KiB
 
|l2 desc=4-way set associative
 
}}
 
 
== Memory controller ==
 
{{memory controller
 
|type=DDR2-533
 
|ecc=Yes
 
|max mem=2 GiB
 
|controllers=1
 
|channels=1
 
|width=32 bit
 
|max bandwidth=1.986 GiB/s
 
|bandwidth schan=1.986 GiB/s
 
}}
 
 
== Expansions ==
 
{{expansions
 
|pci width=32 bit
 
|pci clock=66.66 MHz
 
|pci rate=254.31 MiB/s
 
|pci extra=host or slave
 
|usb revision=2.0
 
|usb ports=1
 
|usb rate=60 MB/s
 
|usb extra=host / PHY
 
|uart=yes
 
|uart ports=2
 
|gp io=Yes
 
}}
 
 
== Networking ==
 
{{network
 
|mii opts=Yes
 
|rgmii=yes
 
|rgmii ports=3
 
|pcm=yes
 
}}
 
 
== Hardware Accelerators ==
 
{{accelerators
 
|encryption=Yes
 
|encryption type=DES, 3DES, AES up to 256 bit, SHA1, SHA-2 up to SHA-512, RSA, DH
 
|tcp=Yes
 
|qos=Yes
 
}}
 
 
== Block diagram ==
 
[[File:cn3010 block diagram.png|750px]]
 
 
== Datasheet ==
 
* [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]]
 

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base frequency400 MHz (0.4 GHz, 400,000 kHz) +
core count1 +
core namecnMIPS +
designerCavium +
familyOCTEON +
first announcedJanuary 30, 2006 +
first launchedMay 1, 2006 +
full page namecavium/octeon/cn3010-400bg525-scp +
has ecc memory supporttrue +
has hardware accelerators for cryptographytrue +
has hardware accelerators for network quality of service processingtrue +
has hardware accelerators for tcp packet processingtrue +
instance ofmicroprocessor +
isaMIPS64 +
isa familyMIPS +
l1$ size24 KiB (24,576 B, 0.0234 MiB) +
l1d$ description64-way set associative +
l1d$ size8 KiB (8,192 B, 0.00781 MiB) +
l1i$ description2-way set associative +
l1i$ size16 KiB (16,384 B, 0.0156 MiB) +
l2$ description4-way set associative +
l2$ size0.125 MiB (128 KiB, 131,072 B, 1.220703e-4 GiB) +
ldateMay 1, 2006 +
main imageFile:cn3005-15.png +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
max memory2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) +
max memory bandwidth1.986 GiB/s (2,033.664 MiB/s, 2.132 GB/s, 2,132.451 MB/s, 0.00194 TiB/s, 0.00213 TB/s) +
max memory channels1 +
microarchitecturecnMIPS +
model numberCN3010-400 SCP +
nameCavium CN3010-400 SCP +
part numberCN3010-400BG525-SCP +
power dissipation3 W (3,000 mW, 0.00402 hp, 0.003 kW) +
process130 nm (0.13 μm, 1.3e-4 mm) +
seriesCN3000 +
smp max ways1 +
supported memory typeDDR2-533 +
technologyCMOS +
thread count1 +
word size64 bit (8 octets, 16 nibbles) +