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{{cavium title|CN3005-500 CP}} | {{cavium title|CN3005-500 CP}} | ||
− | {{ | + | {{mpu |
| name = Cavium CN3005-500 CP | | name = Cavium CN3005-500 CP | ||
| no image = | | no image = | ||
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| designer = Cavium | | designer = Cavium | ||
| manufacturer = TSMC | | manufacturer = TSMC | ||
− | | model number = CN3005 | + | | model number = CN3005 |
| part number = CN3005-500BG350-CP | | part number = CN3005-500BG350-CP | ||
+ | | part number 1 = | ||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
− | |||
| market = Embedded | | market = Embedded | ||
| first announced = January 30, 2006 | | first announced = January 30, 2006 | ||
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| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
− | | release price = | + | | release price = $39 |
| family = OCTEON | | family = OCTEON | ||
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| max memory addr = | | max memory addr = | ||
− | + | | electrical = Yes | |
| power = 4 W | | power = 4 W | ||
| v core = | | v core = | ||
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| socket 0 type = | | socket 0 type = | ||
}} | }} | ||
− | The '''CN3005-500 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[ | + | The '''CN3005-500 CP''' is a {{arch|64}} [[single-core]] [[MIPS]] communication [[microprocessor]] (CP) designed by [[Cavium]] and introduced in [[2005]]. This processor, which incorporates a single {{cavium|cnMIPS|l=arch}} core, operates at 500 MHz and dissipates 4 Watts. This processors includes a number of hardware communication accelerators including units for high-performance packet I/O processing, QoS, and TCP acceleration. This MPU supports up to 2 GiB of DDR2-533 ECC memory. |
== Cache == | == Cache == | ||
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{{memory controller | {{memory controller | ||
|type=DDR2-533 | |type=DDR2-533 | ||
− | |ecc= | + | |ecc=Yes |
|max mem=2 GiB | |max mem=2 GiB | ||
|controllers=1 | |controllers=1 | ||
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|gmii=yes | |gmii=yes | ||
|gmii ports=1 | |gmii ports=1 | ||
+ | |pcm=yes | ||
}} | }} | ||
− | == | + | == Features == |
− | + | Hardware acceleration units: | |
− | + | * Hardware implementation for common security algorithms: | |
− | + | ** DES, 3DES, AES (up to 256 bit), SHA1, SHA-2 up to SHA-512, RSA, DH | |
− | + | * QoS | |
− | + | * TCP Acceleration | |
− | |||
− | |||
== Datasheet == | == Datasheet == | ||
* [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]] | * [[:File:octeon cn30xx product brief.pdf|OCTEON CN30XX Processors Product Brief]] |
Facts about "CN3005-500 CP - Cavium"
base frequency | 500 MHz (0.5 GHz, 500,000 kHz) + |
core count | 1 + |
core name | cnMIPS + |
designer | Cavium + |
family | OCTEON + |
first announced | January 30, 2006 + |
first launched | May 1, 2006 + |
full page name | cavium/octeon/cn3005-500bg350-cp + |
has ecc memory support | false + |
has hardware accelerators for network quality of service processing | true + |
has hardware accelerators for tcp packet processing | true + |
instance of | microprocessor + |
isa | MIPS64 + |
isa family | MIPS + |
l1$ size | 24 KiB (24,576 B, 0.0234 MiB) + |
l1d$ description | 64-way set associative + |
l1d$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
l1i$ description | 2-way set associative + |
l1i$ size | 16 KiB (16,384 B, 0.0156 MiB) + |
l2$ description | 2-way set associative + |
l2$ size | 0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) + |
ldate | May 1, 2006 + |
main image | + |
manufacturer | TSMC + |
market segment | Embedded + |
max cpu count | 1 + |
max memory | 2,048 MiB (2,097,152 KiB, 2,147,483,648 B, 2 GiB, 0.00195 TiB) + |
max memory bandwidth | 0.993 GiB/s (1,017 MiB/s, 1.066 GB/s, 1,066.402 MB/s, 9.698868e-4 TiB/s, 0.00107 TB/s) + |
max memory channels | 1 + |
microarchitecture | cnMIPS + |
model number | CN3005-500 CP + |
name | Cavium CN3005-500 CP + |
part number | CN3005-500BG350-CP + |
power dissipation | 4 W (4,000 mW, 0.00536 hp, 0.004 kW) + |
process | 130 nm (0.13 μm, 1.3e-4 mm) + |
series | CN3000 + |
smp max ways | 1 + |
supported memory type | DDR2-533 + |
technology | CMOS + |
thread count | 1 + |
word size | 64 bit (8 octets, 16 nibbles) + |