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Difference between revisions of "cavium/microarchitectures/thunderx1"
< cavium
(added rough description of original ThunderX from public sources) |
(No difference)
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Revision as of 20:35, 3 December 2018
| Edit Values | |
| ThunderX1 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Cavium |
| Manufacturer | GlobalFoundries |
| Introduction | 2014 |
| Process | 28 nm |
| Core Configs | 24, 48 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | ? |
| Decode | 4? |
| Instructions | |
| ISA | ARMv8.1 |
| Extensions | NEON, TrustZone |
| Cache | |
| L1I Cache | 78 KiB/core 37?-way set associative |
| L1D Cache | 32 KiB/core ?-way set associative |
| L2 Cache | 16 MiB/socket ?-way set associative |
The microarchitecture of the original custom-designed Cavium ThunderX processor might be called ThunderX1 for the purposes of this wiki. [1] [2]
Retrieved from "https://en.wikichip.org/w/index.php?title=cavium/microarchitectures/thunderx1&oldid=84585"
Facts about "ThunderX1 - Microarchitectures - Cavium"
| codename | ThunderX1 + |
| core count | 24 + and 48 + |
| designer | Cavium + |
| first launched | 2014 + |
| full page name | cavium/microarchitectures/thunderx1 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv8.1 + |
| manufacturer | GlobalFoundries + |
| microarchitecture type | CPU + |
| name | ThunderX1 + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |
