From WikiChip
Difference between revisions of "baikal/baikal-t1"
< baikal

(Expansions)
(Cache)
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== Cache ==
 
== Cache ==
 
{{cache info
 
{{cache info
|l1i cache=32 KB
+
|l1i cache=32 KiB
|l1i break=1x32 KB
+
|l1i break=1x32 KiB
 
|l1i desc=4-way set associative
 
|l1i desc=4-way set associative
 
|l1i extra=(per core, write-back)
 
|l1i extra=(per core, write-back)
|l1d cache=32 KB
+
|l1d cache=32 KiB
|l1d break=1x32 KB
+
|l1d break=1x32 KiB
 
|l1d desc=4-way set associative
 
|l1d desc=4-way set associative
 
|l1d extra=(per core, write-back)
 
|l1d extra=(per core, write-back)
|l2 cache=1 MB
+
|l2 cache=1 MiB
|l2 break=2x512 KB
+
|l2 break=2x512 KiB
 
|l2 desc=4-way set associative
 
|l2 desc=4-way set associative
 
|l2 extra=(shared)
 
|l2 extra=(shared)

Revision as of 23:43, 20 September 2016

Template:mpu The Baikal-T1 is a 32-bit dual-core microprocessor introduced by Baikal Electronics in 2015. The chip entered mass production in early 2016. The Baikal-T1 incorporates two of Imagination Technologies high-performance P5600 cores implementing the MIPS32 ISA up to release 5.

The chip consumes less than 5W and can be used in fanless designs.

Cache

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 4-way set associative (per core, write-back)
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 4-way set associative (per core, write-back)
L2$ 1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
2x512 KiB 4-way set associative (shared)

Memory controller

Integrated Memory Controller
Type DDR3-1600
Controllers 1
Channels 2
ECC Support Yes

Expansions

Template:mpu expansions

Networking

The Baikal-T1 has support for 1x10Gb and 2x1Gb Ethernet ports.


Networking
1000Base-T Yes
10GBase-T Yes
l1d$ description4-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description4-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +
l2$ description4-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) +