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{{microarchitecture
 
{{microarchitecture
 
|atype=CPU
 
|atype=CPU
|name=Neoverse N1
+
|name=Ares
 
|designer=ARM Holdings
 
|designer=ARM Holdings
 
|manufacturer=TSMC
 
|manufacturer=TSMC
 
|introduction=February 20, 2019
 
|introduction=February 20, 2019
 
|process=7 nm
 
|process=7 nm
|cores=4
 
|cores 2=8
 
|cores 3=16
 
|cores 4=32
 
|cores 5=64
 
|cores 6=96
 
|cores 7=128
 
|type=Superscalar
 
|type 2=Superpipeline
 
 
|oooe=Yes
 
|oooe=Yes
 
|speculative=Yes
 
|speculative=Yes
 
|renaming=Yes
 
|renaming=Yes
|stages=11
 
|decode=4-way
 
|isa=ARMv8.2
 
|l1i=64 KiB
 
|l1i per=core
 
|l1i desc=4-way set associative
 
|l1d=64 KiB
 
|l1d per=core
 
|l1d desc=4-way set associative
 
|l2=512-1 MiB
 
|l2 per=core
 
|l2 desc=8-way set associative
 
|l3=2-4 MiB
 
|l3 per=core duplex
 
|l3 desc=16-way set associative
 
 
|predecessor=Cosmos
 
|predecessor=Cosmos
 
|predecessor link=arm_holdings/cosmos
 
|predecessor link=arm_holdings/cosmos
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== History ==
 
== History ==
 
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
 
[[File:arm server roadmap techcon 2018.jpg|thumb|right|Arm's server roadmap.]]
The Neoverse N1, formerly Ares, is the first [[Arm]] design to specifically target the infrastructure market, serving as the successor to the {{armh|Cosmos|Cosmos platform}} which used the same cores as the client platform. The N1 was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019.
+
Ares was first announced by Drew Henry, Arm’s SVP and GM of Infrastructure Business Unit, at his TechCon 2018 keynote. Ares was officially unveiled on February 20, 2019.
  
 
== Release Dates ==
 
== Release Dates ==
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== Process Technology ==
 
== Process Technology ==
 
Ares specifically takes advantage of the power and area advantages of the [[7 nm process]].
 
Ares specifically takes advantage of the power and area advantages of the [[7 nm process]].
 
== Compiler Support ==
 
{| class="wikitable"
 
|-
 
! Compiler !! Arch-Specific || Arch-Favorable || Arch-Target
 
|-
 
| [[GCC]] || <code>-march=armv8.2-a</code> || <code>-mtune=neoverse-n1</code> || <code>-mcpu=neoverse-n1</code>
 
|-
 
| [[LLVM]] || <code>-march=armv8.2-a</code> || <code>-mtune=neoverse-n1</code> || <code>-mcpu=neoverse-n1</code>
 
|}
 
  
 
== Architecture ==
 
== Architecture ==
 
The Neoverse N1 core is almost identical to the {{\\|Cortex-A76}} but features a number of enhancements for infrastructure workload.
 
The Neoverse N1 core is almost identical to the {{\\|Cortex-A76}} but features a number of enhancements for infrastructure workload.
  
* [[ARMv8.2]]
 
 
* [[7 nm process]]
 
* [[7 nm process]]
 
* Core
 
* Core
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== Overview ==
 
== Overview ==
[[File:neoverse n1 overview.svg|right|500px|thumb|Neoverse N1 Typical SoC]]
+
{{empty section}}
Formerly known as Ares, the Neoverse N1 is the first ground-up Arm microarchitecture design that targets infrastructure, targetting a wide range of markets from the [[edge computing|edge]] to [[hyperscalers]] data centers. Departing from Arm's low-power {{armh|cortex|mobile cores}}, the N1 targets high-performance server workloads at higher TDPs and higher compute power. Compared to the prior {{armh|Cosmos|l=arch}} platform, the Neoverse N1 is said to deliver a significant uplift in single-thread performance.
 
 
 
The Neoverse N1 is designed to enable Arm partners rapid development of high-performance server products. The N1 features an 11-stage [[out-of-order]] core with private [[L1]] and [[L2]] caches. The core is intended to leverage Arm's {{armh|Coherent Mesh Network}} 600 (CMN-600) [[interconnect]] to scale from as little as a [[quad-core]] design to as much as [[128 cores]] and from a single [[DDR]] channel all the way up to eight channels, depending on the kind of workload being addressed. Extending the base design is a framework for [[multiprocessing]] support as well as [[chiplets]] support which can be used by companies who are looking to improve [[yield]] and manufacturability with large SoC designs. The N1 is also designed to work seamlessly with the {{\\|Neoverse E1}} which was introduced at the same time as N1 but is optimized for high throughput multithreaded workloads.
 
  
 
== Core ==
 
== Core ==
The Neoverse N1 features an 11-stage accordion integer pipeline.
+
{{empty section}}
 
 
 
 
::[[File:neoverse n1 pipeline.svg|600px]]
 
  
 
== Die ==
 
== Die ==
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* 1.2 mm² die size (1C + 512 KiB L2)
 
* 1.2 mm² die size (1C + 512 KiB L2)
 
* 1.4 mm² die size (1C + 1 MiB L2)
 
* 1.4 mm² die size (1C + 1 MiB L2)
* 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 GHz (1.0 V)
+
* 1 W @ 2.6 GHz (0.75 V), 1.8 W @ 3.1 W (1.0 V)
  
  
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* Drew Henry, direct communication
 
* Drew Henry, direct communication
 
* Most of the technical details were obtained directly from Arm
 
* Most of the technical details were obtained directly from Arm
 
== Documents ==
 
* [[:File:arm neoverse n1 sog.pdf|Neoverse N1 Software Optimization Guide]]
 
* [[:File:arm neoverse n1 trm.pdf|Neoverse N1 Technical Reference Manual]]
 

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codenameNeoverse N1 +
core count4 +, 8 +, 16 +, 32 +, 64 +, 96 + and 128 +
designerARM Holdings +
first launchedFebruary 20, 2019 +
full page namearm holdings/microarchitectures/neoverse n1 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +
microarchitecture typeCPU +
nameNeoverse N1 +
pipeline stages11 +
process7 nm (0.007 μm, 7.0e-6 mm) +