Editing arm holdings/microarchitectures/cortex-a8

{{armh title|Cortex-A8|arch}}
{{microarchitecture
|atype=CPU
|name=Cortex-A8
|designer=ARM Holdings
|manufacturer=TSMC
|introduction=October 5, 2005
|process=65 nm
|process 2=45 nm
|type=Superscalar
|type 2=Pipelined
|oooe=No
|speculative=Yes
|stages=13
|decode=2-way
|isa=ARMv7
|extension=NEON
|extension 2=TrustZone
|extension 3=Thumb-2
|extension 4=Jazelle-RCT
|extension 5=VFPv3
|predecessor=ARM11
|predecessor link=arm_holdings/microarchitectures/arm11
|successor=Cortex-A9
|successor link=arm_holdings/microarchitectures/cortex-a9
}}
'''Cortex-A8''' (codename '''Tiger''') is the successor to the {{armh|ARM11|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center.

== Architecture ==
The Cortex-A8 was the first application processor from the {{armh|Cortex}} family. It is also [[Arm]]'s first superscalar, dual-issue microprocessor.

=== Key changes from {{\\|ARM11}} ===
* [[65 nm process]] (from [[90 nm]])
* [[ARMv7]] (from [[ARMv6]])
** Support for {{arm|NEON}} (ASIMD)
** {{arm|TrustZone}}
** {{arm|Thumb-2}}
** {{arm|Jazelle-RCT}} (Realtime Compilation Target)
* ARM reported 2.0 DMIPS/MHz (up from 1.2 DMIPS/MHz)
** Average IPC reported is 0.9 (based on SPECint95, EEMBC, Mediabench, and others)
* First [[superscalar]] design
** dual-issue (from single-issue)
** in-order
** 13-stage pipeline (up from 8 stages)
** Targets frequency up to 1 GHz
* First NEON implementation
** 10-stage pipeline
* Dedicated private L2 cache

=== Block Diagram ===
{{empty section}}

=== Memory Hierarchy ===
* Cache
** L1I Cache
*** 16 KiB OR 32 KiB (configurable)
*** 4-way set associative
*** 64 B line size
*** [[Random replacement policy]]
** L1D Cache
*** 16 KiB OR 32 KiB (configurable)
*** 4-way set associative
*** 64 B line size
*** [[Random replacement policy]]
** L2 Cache
*** 0 KiB OR 128 KiB OR 1 MiB (configurable)
*** 8-way set associative
*** 64 B line size
*** Optional Parity and ECC

* TLB
** ITLB
*** 32-entry, fully-associative
*** 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes
** DTLB
*** 32-entry, fully-associative
*** 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes

== Die ==
* [[65 nm process]]
* Up to 1 GHz
* 4 mm² (core only, no NEON, L2 cache, and embedded trace)
* <= 300 mW
@@ Line 26: / Line 26: @@
 }}
 '''Cortex-A8''' (codename '''Tiger''') is the successor to the {{armh|ARM11|l=arch}}, a low-power performance [[ARM]] [[microarchitecture]] designed by [[ARM Holdings]] for the mobile market. This microarchitecture is designed as an [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. The Cortex-A8 was designed by the Arm Austin design center.
-== Compiler support ==
-{| class="wikitable"
-|-
-! Compiler !! Arch-Specific || Arch-Favorable
-|-
-| [[Arm Compiler]] || <code>-mcpu=cortex-a8</code> || <code>-mtune=cortex-a8</code>
-|-
-| [[GCC]] || <code>-mcpu=cortex-a8</code> || <code>-mtune=cortex-a8</code>
-|-
-| [[LLVM]] || <code>-mcpu=cortex-a8</code> || <code>-mtune=cortex-a8</code>
-|}
-One can specify {{arm|NEON}} support using the <code>-mfpu=neon</code> option. Note that GCC will not generate floating-point operations for auto-vectorization constructs because [[NEON]], under [[ARMv7]], is not fully [[IEEE 754]]-compliant. It's possible to use <code>-funsafe-math-optimizations</code> to circumvent that behavior.
 == Architecture ==
@@ Line 48: / Line 34: @@
 * [[ARMv7]] (from [[ARMv6]])
 ** Support for {{arm|NEON}} (ASIMD)
-** {{arm|VFPv3}} (from {{arm|VFPv2}})
 ** {{arm|TrustZone}}
 ** {{arm|Thumb-2}}
@@ Line 64: / Line 49: @@
 === Block Diagram ===
-[[File:cortex-a8 block diagram.svg|900px]]
+{{empty section}}
 === Memory Hierarchy ===
@@ Line 91: / Line 76: @@
 *** 32-entry, fully-associative
 *** 4 KiB, 64 KiB, 1 MiB, and 16 MiB page sizes
-== Licensees ==
-Arm named the following companies as licensees.
-{{collist
-|count = 3
-|
-* [[Broadcom]]
-* [[Freescale]]
-* [[Panasonic]]
-* [[Samsung]]
-* [[STMicroelectronics]]
-* [[Texas Instruments]]
-* [[PMC-Sierra]]
-* [[ZiiLABS]]
-}}
 == Die ==
-* [[65 nm process]] (LP)
+* [[65 nm process]]
-* Up to 650 MHz
+* Up to 1 GHz
-* 4 mm² (with cache)
+* 4 mm² (core only, no NEON, L2 cache, and embedded trace)
-* 3 mm² (without cache)
-* 0.59 mW/MHz
 * <= 300 mW
-* [[65 nm process]] (GP)
-* Up to 1,000 MHz
-* 4 mm² (with cache)
-* 3 mm² (without cache)
-* 0.45 mW/MHz
codename	Cortex-A8 +
designer	ARM Holdings +
first launched	October 5, 2005 +
full page name	arm holdings/microarchitectures/cortex-a8 +
instance of	microarchitecture +
instruction set architecture	ARMv7 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Cortex-A8 +
pipeline stages	13 +
process	65 nm (0.065 μm, 6.5e-5 mm) + and 45 nm (0.045 μm, 4.5e-5 mm) +