From WikiChip
Editing arm holdings/microarchitectures/cortex-a76
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 99: | Line 99: | ||
*** 64 KiB, 4-way set associative | *** 64 KiB, 4-way set associative | ||
*** 64-byte cache lines | *** 64-byte cache lines | ||
− | *** | + | *** optional parity protection |
− | |||
** L1D Cache | ** L1D Cache | ||
*** 64 KiB, 4-way set associative | *** 64 KiB, 4-way set associative | ||
*** 64-byte cache lines | *** 64-byte cache lines | ||
*** 4-cycle fastest load-to-use latency | *** 4-cycle fastest load-to-use latency | ||
− | *** | + | *** optional ECC protection per 32 bits |
− | |||
** L2 Cache | ** L2 Cache | ||
*** 256 KiB OR 512 KiB (2 banks) | *** 256 KiB OR 512 KiB (2 banks) | ||
Line 114: | Line 112: | ||
*** [[Modified Exclusive Shared Invalid]] (MESI) coherency | *** [[Modified Exclusive Shared Invalid]] (MESI) coherency | ||
*** Strictly inclusive of the L1 data cache & non-inclusive of the L1 instruction cache | *** Strictly inclusive of the L1 data cache & non-inclusive of the L1 instruction cache | ||
− | |||
** L3 Cache | ** L3 Cache | ||
*** 2 MiB to 4 MiB, 16-way set associative | *** 2 MiB to 4 MiB, 16-way set associative |
Facts about "Cortex-A76 - Microarchitectures - ARM"
codename | Cortex-A76 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 31, 2018 + |
full page name | arm holdings/microarchitectures/cortex-a76 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A76 + |
pipeline stages | 13 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |