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== Overview == | == Overview == | ||
− | The Cortex-A76 is a high-performance synthesizable core designed by [[Arm]] as the successor to the {{\\|Cortex-A75}}. It is delivered as Register Transfer Level (RTL) description in Verilog and is designed. This core supports the {{arm|ARMv8.2}} extension as well as a number of other partial extensions. The A76 is a 4-way superscalar out-of-order processor with a private level 1 and level 2 caches. It is designed to be implemented inside the [[DynamIQ Shared Unit]] (DSU) cluster along with other cores | + | The Cortex-A76 is a high-performance synthesizable core designed by [[Arm]] as the successor to the {{\\|Cortex-A75}}. It is delivered as Register Transfer Level (RTL) description in Verilog and is designed. This core supports the {{arm|ARMv8.2}} extension as well as a number of other partial extensions. The A76 is a 4-way superscalar out-of-order processor with a private level 1 and level 2 caches. It is designed to be implemented inside the [[DynamIQ Shared Unit]] (DSU) cluster along with other cores (e.g., with [[little cores]] such as the {{\\|Cortex-A55}}) |
== Core == | == Core == |
Facts about "Cortex-A76 - Microarchitectures - ARM"
codename | Cortex-A76 + |
core count | 1 +, 2 +, 4 +, 6 + and 8 + |
designer | ARM Holdings + |
first launched | May 31, 2018 + |
full page name | arm holdings/microarchitectures/cortex-a76 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8.2 + |
manufacturer | TSMC + |
microarchitecture type | CPU + |
name | Cortex-A76 + |
pipeline stages | 13 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |