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|manufacturer 4=SMIC
 
|manufacturer 4=SMIC
 
|introduction=May 29, 2017
 
|introduction=May 29, 2017
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|process=16 nm
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|process=20 nm
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|process 2=14 nm
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|process 2=16 nm
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|process 3=10 nm
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|process 3=14 nm
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|process 4=7 nm
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|process 4=10 nm
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|process 5=12 nm
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|process 5=
 
|cores=1
 
|cores=1
 
|cores 2=2
 
|cores 2=2
 
|cores 3=3
 
|cores 3=3
 
|cores 4=4
 
|cores 4=4
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|cores 9=8
 
 
|type=In-order
 
|type=In-order
 
|oooe=No
 
|oooe=No
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|speculative=Yes
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|speculative=No
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|renaming=Yes
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|renaming=No
 
|stages=8
 
|stages=8
 
|decode=2-way
 
|decode=2-way
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|isa=ARMv8.2
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|isa=ARMv8
 
|feature=Hardware virtualization
 
|feature=Hardware virtualization
 
|extension=FPU
 
|extension=FPU
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|l1i=8-64 KiB
 
|l1i=8-64 KiB
 
|l1i per=core
 
|l1i per=core
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|l1i desc=4-way set associative
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|l1i desc=2-way set associative
 
|l1d=8-64 KiB
 
|l1d=8-64 KiB
 
|l1d per=core
 
|l1d per=core
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|l2=64-256 KiB
 
|l2=64-256 KiB
 
|l2 per=core
 
|l2 per=core
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|l2 desc=4-way set associative
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|l2 desc=
 
|l3=0-4 MiB
 
|l3=0-4 MiB
 
|l3 per=Cluster
 
|l3 per=Cluster
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|predecessor=Cortex-A53
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|predecessor=Cortex-A7
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|predecessor link=arm_holdings/microarchitectures/cortex-a53
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|predecessor link=arm_holdings/microarchitectures/cortex-a7
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|successor=Cortex-A510
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|successor=Cortex-A55
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|successor link=arm_holdings/microarchitectures/cortex-a510
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|successor link=arm_holdings/microarchitectures/cortex-a55
 
}}
 
}}
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'''Cortex-A55''' (codename '''Ananke''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A53|l=arch}}. The Cortex-A55, which implemented the {{arm|ARMv8.2}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A55 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A75|l=arch}}) in {{armh|DynamIQ big.LITTLE}} configuration to achieve better energy/performance.
 
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Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips.
 
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== Process Technology ==
 
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The Cortex-A55 was primarily designed to make use of [[TSMC]]'s [[16 nm process]] with a [[7 nm]] optimized version set for the end of 2017 or early 2018.
 
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== Architecture ==
 
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The Cortex-A55 is an improved version of the A53 which introduces a number of performance enhancements as well as designed to be implemented based on [[ARM Holding|ARM]]'s {{armh|DynamIQ big.LITTLE}} design.
 
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=== Key changes from {{\\|Cortex-A53}} ===
 
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* Higher performance (ARM claims: up to 2x mem perf, up to 15% less power from A53)
 
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* Implements [[ARMv8.2]] (from ARMv8.0)
 
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* Designed as a cluster of [[single-core|1]] to [[8 cores|8]] cores
 
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** Adds DynamIQ Shared Unit (DSU)
 
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* Branch predictor was re-written
 
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* Memory subsystem
 
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** L2
 
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*** L2 cache is now private to each core (from shared between all cores)
 
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*** Latency was cut by half
 
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*** Now runs at the same frequency as the core
 
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*** Configurable size from 64 KiB to 256 KiB
 
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** L3
 
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*** A new L3 cache was introduced
 
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*** Shared by all cores
 
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*** Configurable size: 0 MiB - 4 MiB
 
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* {{arm|NEON}} is improved
 
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** New instructions
 
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** Up to 16x 8-bit [[integer]] operations per cycle
 
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** Up to 8x 16-bit [[floating point]] per cycle
 
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== Licensees ==
 
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Arm named the following companies as licensees.
 
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{{collist
 
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|count = 3
 
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|
 
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* [[AMD]]
 
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* [[Broadcom]]
 
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* [[HiSilicon]]
 
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* [[STMicroelectronics]]
 
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* [[Samsung]]
 
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* [[MediaTek]]
 
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* [[Huawei]]
 
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* [[Unisoc]]
 
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* [[Amlogic]]
 
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}}
 
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== Die ==
 
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{{empty section}}
 
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== All Cortex-A55 Chips ==
 
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<!-- NOTE:
 
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          This table is generated automatically from the data in the actual articles.
 
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
 
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          created and tagged accordingly.
 
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          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 
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-->
 
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{{comp table start}}
 
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<table class="comptable sortable tc18 tc19 tc20 tc21 tc22 tc23">
 
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="25">List of all Cortex-A55 Chips</th></tr>
 
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr>
 
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{{comp table header 1|cols=Launched, Designer, Family, Core, C, T, L2$, L3$, Frequency, Max Mem, Designer, Name, Frequency}}
 
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{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A55]]
 
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|?full page name
 
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|?model number
 
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|?first launched
 
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|?designer
 
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|?microprocessor family
 
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|?core name
 
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|?core count
 
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|?thread count
 
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|?l2$ size
 
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|?l3$ size
 
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|?base frequency#GHz
 
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|?max memory#GiB
 
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|?integrated gpu designer
 
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|?integrated gpu
 
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|?integrated gpu base frequency
 
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|format=template
 
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|template=proc table 3
 
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|searchlabel=
 
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|sort=microprocessor family, model number
 
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|order=asc,asc
 
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|userparam=15
 
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|mainlabel=-
 
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|limit=100
 
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|valuesep=,
 
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}}
 
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{{comp table count|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A55]]}}
 
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</table>
 
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{{comp table end}}
 

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Facts about "Cortex-A55 - Microarchitectures - ARM"
RDF feed
codenameCortex-A55 +
core count1 +, 2 +, 3 + and 4 +
designerARM Holdings +
first launchedMay 29, 2017 +
full page namearm holdings/microarchitectures/cortex-a55 +
instance ofmicroarchitecture +
instruction set architectureARMv8.2 +
manufacturerTSMC +, Samsung +, GlobalFoundries + and SMIC +
microarchitecture typeCPU +
nameCortex-A55 +
pipeline stages8 +
process16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) +, 10 nm (0.01 μm, 1.0e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +