From WikiChip
Editing arm holdings/microarchitectures/cortex-a53
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 9: | Line 9: | ||
|Max clock rate=2,45GHz boost | |Max clock rate=2,45GHz boost | ||
|introduction=October 30, 2012 | |introduction=October 30, 2012 | ||
− | |process= | + | |process=28 nm |
− | |process 2= | + | |process 2=20 nm |
− | |process 3= | + | |process 3=16 nm |
− | |process 4= | + | |process 4=14 nm |
− | |process 5 | + | |process 5=10 nm |
− | |||
|cores=1 | |cores=1 | ||
|cores 2=2 | |cores 2=2 | ||
Line 45: | Line 44: | ||
|pipeline=Yes | |pipeline=Yes | ||
|issues=2 | |issues=2 | ||
+ | |||
+ | |||
|core names=<!-- Yes if specify --> | |core names=<!-- Yes if specify --> | ||
+ | |||
}} | }} | ||
'''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance. | '''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance. |
Facts about "Cortex-A53 - Microarchitectures - ARM"
codename | Cortex-A53 + |
core count | 1 +, 2 +, 3 + and 4 + |
designer | ARM Holdings + |
first launched | October 30, 2012 + |
full page name | arm holdings/microarchitectures/cortex-a53 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC +, Samsung + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Cortex-A53 + |
pipeline stages | 8 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |