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* 113 mm² die size | * 113 mm² die size | ||
* Mali-T760 (6 EU) | * Mali-T760 (6 EU) | ||
− | * Quad-core Cortex-A53 ([[small cores]]) | + | * Quad-core {{\\|Cortex-A53}} ([[small cores]]) |
** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2 | ** 32 KiB L1I$ and 32 KiB L1D$ per core, and a shared 256 KiB L2 | ||
** 4.4 mm² per cluster | ** 4.4 mm² per cluster | ||
*** ~1 mm² per core | *** ~1 mm² per core | ||
*** ~0.55 mm² for 256 KiB L2 cache | *** ~0.55 mm² for 256 KiB L2 cache | ||
− | * Quad-core | + | * Quad-core Cortex-A57 ([[big cores]]) |
** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2 | ** 48KB L1I$ and 32KB L1D$ per core, and a shared 2 MiB L2 | ||
** 15.85 mm² per cluster | ** 15.85 mm² per cluster |
Facts about "Cortex-A53 - Microarchitectures - ARM"
codename | Cortex-A53 + |
core count | 1 +, 2 +, 3 + and 4 + |
designer | ARM Holdings + |
first launched | October 30, 2012 + |
full page name | arm holdings/microarchitectures/cortex-a53 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC +, Samsung + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Cortex-A53 + |
pipeline stages | 8 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |