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|name=Cortex-A53 | |name=Cortex-A53 | ||
|designer=ARM Holdings | |designer=ARM Holdings | ||
− | |manufacturer=TSMC | + | |manufacturer=TSMC, Samsung |
− | + | |introduction=July 2014 | |
− | + | |process=28 nm | |
− | + | |process 2=20 nm | |
− | |introduction= | + | |process 3=16 nm |
− | |process= | + | |process 4=14 nm |
− | |process 2= | + | |process 5=10 nm |
− | |process 3= | ||
− | |process 4= | ||
− | |process 5 | ||
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|cores=1 | |cores=1 | ||
|cores 2=2 | |cores 2=2 | ||
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|type=In-order | |type=In-order | ||
|oooe=No | |oooe=No | ||
− | |speculative= | + | |speculative=No |
|renaming=No | |renaming=No | ||
|stages=8 | |stages=8 | ||
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|pipeline=Yes | |pipeline=Yes | ||
|issues=2 | |issues=2 | ||
+ | |inst=Yes | ||
+ | |cache=Yes | ||
|core names=<!-- Yes if specify --> | |core names=<!-- Yes if specify --> | ||
+ | |succession=Yes | ||
}} | }} | ||
'''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance. | '''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A7|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance. | ||
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== Process Technology == | == Process Technology == | ||
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== Architecture == | == Architecture == | ||
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== Die == | == Die == | ||
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== All Cortex-A53 Chips == | == All Cortex-A53 Chips == | ||
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<tr class="comptable-header"><th> </th><th colspan="25">List of all Cortex-A53 Chips</th></tr> | <tr class="comptable-header"><th> </th><th colspan="25">List of all Cortex-A53 Chips</th></tr> | ||
<tr class="comptable-header"><th> </th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr> | <tr class="comptable-header"><th> </th><th colspan="10">Main processor</th><th colspan="3">IGP</th></tr> | ||
− | {{comp table header 1|cols=Launched, Designer, Family | + | {{comp table header 1|cols=Launched, Designer, Family, Core, C, T, L2$, L3$, Frequency, Max Mem, Designer, Name, Frequency}} |
{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]] | {{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]] | ||
|?full page name | |?full page name | ||
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|?designer | |?designer | ||
|?microprocessor family | |?microprocessor family | ||
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|?core name | |?core name | ||
|?core count | |?core count | ||
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</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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Facts about "Cortex-A53 - Microarchitectures - ARM"
codename | Cortex-A53 + |
core count | 1 +, 2 +, 3 + and 4 + |
designer | ARM Holdings + |
first launched | October 30, 2012 + |
full page name | arm holdings/microarchitectures/cortex-a53 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC +, Samsung + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Cortex-A53 + |
pipeline stages | 8 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |