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{{armh title|Cortex-A53|arch}} | {{armh title|Cortex-A53|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
− | + | | name = Cortex-A53 | |
− | |name=Cortex-A53 | + | | designer = ARM Holdings |
− | |designer=ARM Holdings | + | | manufacturer = |
− | |manufacturer= | + | | introduction = July 2014 |
− | + | | phase-out = | |
− | + | | process = 28 nm | |
− | + | | process 2 = 20 nm | |
− | |introduction= | + | | process 3 = 16 nm |
− | | | + | | process 4 = 14 nm |
− | |process | + | | process 5 = 10 nm |
− | |process | + | | cores = 1 |
− | |process | + | | cores 2 = 2 |
− | |process | + | | cores 3 = 3 |
− | |process | + | | cores 4 = 4 |
− | |cores=1 | ||
− | |cores 2=2 | ||
− | |cores 3=3 | ||
− | |cores 4=4 | ||
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− | + | | pipeline = Yes | |
+ | | type = | ||
+ | | type 2 = | ||
+ | | type N = | ||
+ | | OoOE = No | ||
+ | | speculative = No | ||
+ | | renaming = | ||
+ | | isa = ARMv8 | ||
+ | | stages = 8 | ||
+ | | stages min = | ||
+ | | stages max = | ||
+ | | issues = 2 | ||
− | == | + | | inst = Yes |
− | + | | feature = Hardware virtualization | |
+ | | extension = NEON | ||
+ | | extension 2 = TrustZone | ||
+ | | extension N = | ||
− | = | + | | cache = Yes |
− | + | | l1i = 8-64 KiB | |
− | | | + | | l1i per = core |
− | + | | l1i desc = 2-way set associative | |
− | |- | + | | l1d = 8-64 KiB |
− | | | + | | l1d per = core |
− | | | + | | l1d desc = 4-way set associative |
− | | | + | | l2 = 128 KiB - 2 MiB |
− | | | + | | l2 per = cluster |
+ | | l2 desc = 16-way set associative | ||
+ | | l3 = | ||
+ | | l3 per = | ||
+ | | l3 desc = | ||
− | + | | core names = <!-- Yes if specify --> | |
+ | | core name = | ||
+ | | core name 2 = | ||
+ | | core name N = | ||
− | + | | succession = Yes | |
− | + | | predecessor = Cortex-A9 | |
− | + | | predecessor link = arm_holdings/microarchitectures/cortex-a9 | |
+ | | successor = | ||
+ | | successor link = | ||
+ | | successor 2 = | ||
+ | | successor 2 link = | ||
+ | }} | ||
+ | '''Cortex-A53''' (formerly '''Apollo''') is an ultra-high efficiency [[microarchitecture]] designed by [[ARM Holdings]] as a successor to the {{armh|Cortex-A9|l=arch}}. The Cortex-A53, which implemented the {{arm|ARMv8}} ISA, is typically found in entry-level smartphone and other embedded devices. Often A53 cores are combined with higher performance processors (e.g. based on {{armh|Cortex-A57|l=arch}} or {{armh|Cortex-A72|l=arch}}) in {{armh|big.LITTLE}} configuration to achieve better energy/performance. | ||
+ | Note that this microarchitecture is designed as a synthesizable [[IP core]] and is sold to other semiconductor companies to be implemented in their own chips. | ||
+ | == Process Technology == | ||
+ | {{empty section}} | ||
== Architecture == | == Architecture == | ||
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{{empty section}} | {{empty section}} | ||
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== Die == | == Die == | ||
− | + | {{empty section}} | |
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== All Cortex-A53 Chips == | == All Cortex-A53 Chips == | ||
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Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
--> | --> | ||
− | + | <table class="wikitable sortable"> | |
− | <table class=" | + | <tr><th colspan="10" style="background:#D6D6FF;">Cortex-A53 Chips</th></tr> |
− | <tr | + | <tr><th colspan="8">Main processor</th><th colspan="2">IGP</th></tr> |
− | <tr | + | <tr><th>Model</th><th>Designer</th><th>Family</th><th>Core</th><th>Launched</th><th>Cores</th><th>Frequency</th><th>Max Mem</th><th>Name</th><th>Freq</th></tr> |
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{{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]] | {{#ask: [[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]] | ||
|?full page name | |?full page name | ||
|?model number | |?model number | ||
− | |||
|?designer | |?designer | ||
|?microprocessor family | |?microprocessor family | ||
− | |||
|?core name | |?core name | ||
+ | |?first launched | ||
|?core count | |?core count | ||
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|?base frequency#GHz | |?base frequency#GHz | ||
|?max memory#GiB | |?max memory#GiB | ||
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|?integrated gpu | |?integrated gpu | ||
|?integrated gpu base frequency | |?integrated gpu base frequency | ||
+ | |?has simultaneous multithreading | ||
|format=template | |format=template | ||
− | |template=proc table | + | |template=proc table 2 |
|searchlabel= | |searchlabel= | ||
− | + | |userparam=11 | |
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− | |userparam= | ||
|mainlabel=- | |mainlabel=- | ||
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}} | }} | ||
− | {{ | + | {{table count|col=11|ask=[[Category:all microprocessor models]] [[microarchitecture::Cortex-A53]]}} |
</table> | </table> | ||
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Facts about "Cortex-A53 - Microarchitectures - ARM"
codename | Cortex-A53 + |
core count | 1 +, 2 +, 3 + and 4 + |
designer | ARM Holdings + |
first launched | October 30, 2012 + |
full page name | arm holdings/microarchitectures/cortex-a53 + |
instance of | microarchitecture + |
instruction set architecture | ARMv8 + |
manufacturer | TSMC +, Samsung + and GlobalFoundries + |
microarchitecture type | CPU + |
name | Cortex-A53 + |
pipeline stages | 8 + |
process | 40 nm (0.04 μm, 4.0e-5 mm) +, 28 nm (0.028 μm, 2.8e-5 mm) +, 20 nm (0.02 μm, 2.0e-5 mm) +, 16 nm (0.016 μm, 1.6e-5 mm) +, 14 nm (0.014 μm, 1.4e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |