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Latest revision | Your text | ||
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=== Key changes from {{\\|ARM3}} === | === Key changes from {{\\|ARM3}} === | ||
* [[0.8 µm process]] (from [[1.5 µm]]) | * [[0.8 µm process]] (from [[1.5 µm]]) | ||
− | |||
* 32-bit address space (from {{arm|26-bit}}) | * 32-bit address space (from {{arm|26-bit}}) | ||
** Can map 4 GiB of memory | ** Can map 4 GiB of memory | ||
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** Their own separate registers | ** Their own separate registers | ||
** Backwards compatibility mode | ** Backwards compatibility mode | ||
− | *** 26-bit Mode | + | *** 26-bit Mode + 32-bit Mode |
− | * New Modes | + | * New Modes |
** Abort (abt) | ** Abort (abt) | ||
** Undefined (und) | ** Undefined (und) |
Facts about "ARM6 - Microarchitectures - ARM"
codename | ARM4 + |
core count | 1 +, 4 +, 6 + and 8 + |
designer | 1 + and ARM Holdings + |
full page name | arm holdings/microarchitectures/arm6 + |
instance of | microarchitecture + |
instruction set architecture | ARMv3 +, ARMv4 + and ARMv6 + |
manufacturer | GEC-Plessey Semiconductors +, Sharp + and VLSI Technology + |
microarchitecture type | CPU + |
name | ARM4 + |
phase-out | 0202 JL + |
pipeline stages | 3 + |
pipeline stages (min) | 12 + |
process | 800 nm (0.8 μm, 8.0e-4 mm) + |
processing element count | 4 +, 6 +, 8 + and 2 + |