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== Overview == | == Overview == | ||
− | {{see also|arm/armv3| | + | {{see also|arm/armv3|ARMv3}} |
The ARM6 is a further evolutionary enhancement of the {{acorn|ARM3|l=arch}}. The new chip integrated a number of highly desired features - particularly ones needed by [[Apple]]. The ARM6, departs from all the {{arm|history|previous ARM chips}} by featuring a full 32-bit address and data buses. To {{arm|26-bit|facilitate}} the larger address space, ARM (previously [[Acorn]]) had to move the status flags from the program counter to its own {{arm|CPSR|independent register}}. In total, the ARM6 has 37 registers consisting of 31 {{arch|32}} general-purpose registers and 6 additional status registers. | The ARM6 is a further evolutionary enhancement of the {{acorn|ARM3|l=arch}}. The new chip integrated a number of highly desired features - particularly ones needed by [[Apple]]. The ARM6, departs from all the {{arm|history|previous ARM chips}} by featuring a full 32-bit address and data buses. To {{arm|26-bit|facilitate}} the larger address space, ARM (previously [[Acorn]]) had to move the status flags from the program counter to its own {{arm|CPSR|independent register}}. In total, the ARM6 has 37 registers consisting of 31 {{arch|32}} general-purpose registers and 6 additional status registers. | ||
Facts about "ARM6 - Microarchitectures - ARM"
codename | ARM4 + |
core count | 1 +, 4 +, 6 + and 8 + |
designer | 1 + and ARM Holdings + |
full page name | arm holdings/microarchitectures/arm6 + |
instance of | microarchitecture + |
instruction set architecture | ARMv3 +, ARMv4 + and ARMv6 + |
manufacturer | GEC-Plessey Semiconductors +, Sharp + and VLSI Technology + |
microarchitecture type | CPU + |
name | ARM4 + |
phase-out | 0202 JL + |
pipeline stages | 3 + |
pipeline stages (min) | 12 + |
process | 800 nm (0.8 μm, 8.0e-4 mm) + |
processing element count | 4 +, 6 +, 8 + and 2 + |