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When the MMU is disabled, such as during RESET, the virtual address is the physical address. Note that because the MMU stores the cache control bits (i.e., <code>Cacheable</code>, <code>Updateable</code>), for the chip to use the IDC, the MMU must also be enabled. | When the MMU is disabled, such as during RESET, the virtual address is the physical address. Note that because the MMU stores the cache control bits (i.e., <code>Cacheable</code>, <code>Updateable</code>), for the chip to use the IDC, the MMU must also be enabled. | ||
− | Four types of faults can be generated on the ARM6: Alignment Fault, Translation Fault, Domain Fault, Permission Fault | + | Four types of faults can be generated on the ARM6: Alignment Fault, Translation Fault, Domain Fault, Permission Fault. |
== Die == | == Die == |
Facts about "ARM6 - Microarchitectures - ARM"
codename | ARM4 + |
core count | 1 +, 4 +, 6 + and 8 + |
designer | 1 + and ARM Holdings + |
full page name | arm holdings/microarchitectures/arm6 + |
instance of | microarchitecture + |
instruction set architecture | ARMv3 +, ARMv4 + and ARMv6 + |
manufacturer | GEC-Plessey Semiconductors +, Sharp + and VLSI Technology + |
microarchitecture type | CPU + |
name | ARM4 + |
phase-out | 0202 JL + |
pipeline stages | 3 + |
pipeline stages (min) | 12 + |
process | 800 nm (0.8 μm, 8.0e-4 mm) + |
processing element count | 4 +, 6 +, 8 + and 2 + |