From WikiChip
Difference between revisions of "arm holdings/big.little"
< arm holdings

(Created page with "{{armh title|big.LITTLE}} '''big.LITTLE''' is a single-ISA heterogeneous multi-core architecture designed by Arm to enable the integration of multiple ARM core...")
 
(No difference)

Latest revision as of 11:47, 4 July 2022

big.LITTLE is a single-ISA heterogeneous multi-core architecture designed by Arm to enable the integration of multiple ARM cores of varying PPA characteristics onto a single chip. Arm introduced an enhanced version of this design called DynamIQ big.LITTLE.

Overview[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

DynamIQ big.LITTLE[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.
Retrieved from "https://en.wikichip.org/w/index.php?title=arm_holdings/big.little&oldid=100254"