Semiconductor & Computer Engineering
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Difference between revisions of "arm/armv1"
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{{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}} | {{inst|cols=5|section=<span id="logical_instructions">'''Logical Instructions'''</span>}} | ||
| − | {{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm |col 2=AND immed |col 3 =Rd = {{l| | + | {{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, #imm |col 2=AND immed |col 3 =Rd = {{l|land2|Rn|imm}}}} |
| − | {{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=AND |col 3 =Rd = {{l| | + | {{inst|mn=AND |col 1=AND<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=AND |col 3 =Rd = {{l|land2|Rn|{shifted Rm} }}}} |
| − | {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, #imm |col 2=Bit clear immed |col 3 =Rd = {{l| | + | {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, #imm |col 2=Bit clear immed |col 3 =Rd = {{l|land2|Rn|{{l|not|imm}}}}}} |
| − | {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Bit clear |col 3 =Rd = {{l| | + | {{inst|mn=BIC |col 1=BIC<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Bit clear |col 3 =Rd = {{l|land2|Rn|{{l|not|Rm}}}}}} |
{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, #imm |col 2=Exclusive OR immed |col 3 =Rd = {{l|xor|Rn|imm}}}} | {{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, #imm |col 2=Exclusive OR immed |col 3 =Rd = {{l|xor|Rn|imm}}}} | ||
{{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Exclusive OR |col 3 =Rd = {{l|xor|Rn|{shifted Rm} }}}} | {{inst|mn=EOR |col 1=EOR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Exclusive OR |col 3 =Rd = {{l|xor|Rn|{shifted Rm} }}}} | ||
| + | {{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, #imm |col 2=Logical OR immed |col 3 =Rd = {{l|lor2|Rn|imm}}}} | ||
| + | {{inst|mn=ORR |col 1=ORR<cond>{S} Rd, Rn, Rm{, <shift>} |col 2=Logical OR |col 3 =Rd = {{l|lor2|Rn|{shifted Rm} }}}} | ||
{{inst|mn=xxxxxxx |col 1=xxxxxxxxxxxxxx |col 2=xxxxxxxxxx |col 3 =xxxxxxxxxxxxxxxxx}} | {{inst|mn=xxxxxxx |col 1=xxxxxxxxxxxxxx |col 2=xxxxxxxxxx |col 3 =xxxxxxxxxxxxxxxxx}} | ||
Revision as of 19:04, 27 June 2017
ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.
Overview
The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a program counter which is 26 bits in size allowing for an address space of up to 64 MiB of data.
Registers
There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.
Instruction Listing
The ARMv1 is broken down into 8 classes of instruction:
- Movement Instructions
- Load Instructions
- Store Instructions
- Arithmetic Instructions
- Logical Instructions
- Comparison Instructions
- Branch Instructions
- Miscellaneous Instructions
| ARMv1 ISA | ||||
|---|---|---|---|---|
| Mnemonic | Syntax | Description | Action | |
| Movement Instructions | ||||
| MOV | MOV<cond>{S} Rd, #imm | Move value immed | Rd = immed | |
| MOV | MOV<cond>{S} Rd, Rm, {, <shift>} | Move value | Rd = {shifted Rm} | |
| MVN | MVN<cond>{S} Rd, #imm | Move NOT value immed | Rd = ¬immed | |
| MVN | MVN<cond>{S} Rd, Rm, {, <shift>} | Move NOT value | Rd = ¬{shifted Rm} | |
| Load Instructions | ||||
| LDM | LDM<cond><type> Rn{!}, <reglist>{^} | Load multiple | addr = Rn for each Rd in {reglist}: Rd = [addr] update address based on {type} | |
| LDR | LDR<cond>{B} Rd, [Rn {, #imm}]{!} | Load register immed | Rd = [Rn + imm] If !: Rn = Rn + imm | |
| LDR | LDR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!} | Load register | Rd = [Rn + {shifted Rm} If !: Rn = Rn + {shifted Rm}] | |
| LDR | LDR<cond>{B}{T} Rd, [Rn], #imm | Load register, post index | Rd = [Rn] Rn = Rn + imm | |
| LDR | LDR<cond>{B}{T} Rd, [Rn], Rm {, <shift>} | Load register, post index | Rd = [Rn] Rn = Rn + {shifted Rm} | |
| Store Instructions | ||||
| STR | STR{cond} Rd, address | Store Word | [address] = Rd | |
| STRT | STRT{cond} Rd, address | Store Word, User Mode Privilege | [address] = Rd | |
| STRB | STRB{cond} Rd, address | Store Byte | [address][7:0] = Rd[7:0] | |
| STRBT | STRBT{cond} Rd, address | Store Byte, User Mode Privilege | [address][7:0] = Rd[7:0] | |
| STM | STM{cond}{type} Rn[!], {reglist} | Store Multiple | addr = Rn for each Rd in {reglist}: [addr] = Rd addr += {type} | |
| STM | STM{cond}{type} Rn[!], {reglist}^ | Store Multiple, User Mode Privilege | addr = Rn for each Rd in {reglist}: [addr] = Rd Rn += {type} | |
| Arithmetic Instructions | ||||
| ADC | ADC<cond>{S} Rd, Rn, #imm | Add and carry immed | Rd = Rn + imm + C | |
| ADC | ADC<cond>{S} Rd, Rn, Rm{, <shift>} | Add and carry | Rd = Rn + {shifted Rm} + C | |
| ADD | ADD<cond>S Rd, Rn, #imm | Add immed | Rd = Rn + imm | |
| ADD | ADD<cond>S Rd, Rn, Rm{, <shift>} | Add | Rd = Rn + {shifted Rm} | |
| Logical Instructions | ||||
| AND | AND<cond>{S} Rd, Rn, #imm | AND immed | Rd = Rn & imm | |
| AND | AND<cond>{S} Rd, Rn, Rm{, <shift>} | AND | Rd = Rn & {shifted Rm} | |
| BIC | BIC<cond>{S} Rd, Rn, #imm | Bit clear immed | Rd = Rn & ¬imm | |
| BIC | BIC<cond>{S} Rd, Rn, Rm{, <shift>} | Bit clear | Rd = Rn & ¬Rm | |
| EOR | EOR<cond>{S} Rd, Rn, #imm | Exclusive OR immed | Rd = Rn ⊕ imm | |
| EOR | EOR<cond>{S} Rd, Rn, Rm{, <shift>} | Exclusive OR | Rd = Rn ⊕ {shifted Rm} | |
| ORR | ORR<cond>{S} Rd, Rn, #imm | Logical OR immed | Rd = Rn ∥ imm | |
| ORR | ORR<cond>{S} Rd, Rn, Rm{, <shift>} | Logical OR | Rd = Rn ∥ {shifted Rm} | |
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| Comparison Instructions | ||||
| CMN | CMN<cond> Rn, #imm | Compare negative immed | CPSR flags set on (Rn + imm) | |
| CMN | CMN<cond> Rn, Rm{, <shift>} | Compare negative | CPSR flags set on (Rn + {shifted Rm}) | |
| CMP | CMP<cond> Rn, #imm | Compare immed | CPSR flags set on (Rn - imm) | |
| CMP | CMP<cond> Rn, Rm{, <shift>} | Compare | CPSR flags set on (Rn - {shifted Rm}) | |
| Branch Instructions | ||||
| B | B<cond> #imm | Branch relative | PC = PC + address | |
| BL | BL<cond> #imm | Branch and link relative | LR = RET PC = PC + address | |
| Miscellaneous Instructions | ||||
