From WikiChip
Editing apm/microarchitectures/storm

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 17: Line 17:
 
}}
 
}}
 
'''Storm''' is [[AppliedMicro]] first custom [[ARM]] microarchitecture for servers. Storm-based microprocessors were sold under the {{apm|X-Gene 1}} brand of server microprocessors.
 
'''Storm''' is [[AppliedMicro]] first custom [[ARM]] microarchitecture for servers. Storm-based microprocessors were sold under the {{apm|X-Gene 1}} brand of server microprocessors.
−
 
−
== Codenames ==
 
−
{| class="wikitable"
 
−
|-
 
−
! Codename !! Description
 
−
|-
 
−
| Potenza || codename for the core and memory sub-system
 
−
|}
 
−
 
−
== Technology ==
 
−
Storm is fabricated on TSMC's [[40 nm]] bluk CMOS.
 
−
 
−
== Architecture ==
 
−
 
−
=== Memory Hierarchy ===
 
−
* Cache
 
−
** L1I
 
−
*** 32 KiB, 8-way set associative
 
−
**** Per core
 
−
*** ECC and Parity protection
 
−
** L1D
 
−
*** 32 KiB, 8-way set associative
 
−
**** Per core
 
−
*** 64 B/line
 
−
*** Write-through with [[write-combining]]
 
−
*** ECC and Parity protection
 
−
** L2
 
−
*** 256 KB
 
−
**** Per process module (2 cores)
 
−
***  Inclusive of L1 write-thru data caches
 
−
*** 64 B/line
 
−
*** ECC and Parity protection
 
−
** L3
 
−
*** 8 MiB
 
−
*** 64 B/line
 
−
*** Per chip
 
−
 
−
== Die ==
 
−
=== Complete SoC ===
 
−
* [[40 nm process]]
 
−
 
−
 
−
:[[File:apm storm die.png|600px]]
 
−
 
−
 
−
:[[File:apm storm die (annotated).png|600px]]
 
−
 
−
=== Compute Complex ===
 
−
* 4 PMDs
 
−
 
−
:[[File:apm storm potenza complex.png|700px]]
 
−
=== Potenza Processor Module (PMD) ===
 
−
* 2 cores per module
 
−
* shared L2
 
−
* [[40 nm process]]
 
−
* 84,000,000 transistors
 
−
* 14.8 mm² die size
 
−
 
−
:[[File:apm storm module.png|700px]]
 
−
 
−
:[[File:apm storm module (annotated).png|700px]]
 
−
 
−
== Bibliography ==
 
−
* Paramesh Gopi, Gaurav Singh, Greg Favor. ''"X-Gene: 64-bit ARM CPU and SoC."'' Hot Chips 24 Symposium (HCS), 2012 IEEE. IEEE, 2012.
 
−
* Alfred Yeung, et al. (February, 2014). ''"A 3GHz 64b ARM v8 Processor in 40nm Bulk CMOS Technology"''.
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/apm/microarchitectures/storm"
Facts about "Storm - Microarchitectures - AppliedMicro"
RDF feed
codenameStorm +
core count8 +
designerAppliedMicro +
first launched2011 +
full page nameapm/microarchitectures/storm +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameStorm +
process40 nm (0.04 μm, 4.0e-5 mm) +