Editing apm/microarchitectures/skylark

{{apm title|Skylark|arch}}
{{microarchitecture
|atype=CPU
|name=Skylark
|designer=AppliedMicro
|designer 2=Ampere Computing
|manufacturer=TSMC
|introduction=2018
|process=16 nm
|cores=32
|type=Superscalar
|oooe=Yes
|speculative=Yes
|renaming=Yes
|isa=ARMv8
|predecessor=Shadowcat
|predecessor link=apm/microarchitectures/shadowcat
|successor=Quicksilver
|successor link=ampere computing/microarchitectures/quicksilver
}}
'''Skylark''' is [[AppliedMicro]]'s successor to {{\\|Shadowcat}}, a [[16 nm]] [[ARM]] microarchitecture for servers. This microarcitecture was eventually acquired by [[Ampere Computing]] which has brought it to market under the {{ampere|eMAG}} brand.

== Release Date ==
[[File:apm roadmap x-gene 1-3.png|right|400px]]
Skylark was first announced at [[Hot Chips]] 26 in [[2014]] with the goal of being released around the end of [[2015]] or [[2016]]. In November of 2016, [[AppliedMicro]] was acquired by [[MACOM]]. Samples for Skylark-based processors were finally announced in March 2017. Later the year the architecture designs, team, and other assets were acquired by [[Ampere Computing]] which has finally brought the product to market in early 2018 with mass production planned for mid-2018.

== Technology ==
Skylark is manufactured on [[TSMC]]'s [[16 nm process|16FF+ process]].

== Architecture ==
=== Key changes from {{\\|Shadowcat}} ===
* [[16 nm process|16 nm (16FF+) process]] (from [[28 nm]])
* Faster frequency (3.3 GHz, up from 2.8 GHz)
* 4x core count (32 cores, up from 8)
** 4x processor modules (16 duplexes, up from 4)
** Coherent network improved for large core count
* 4x L3 (32 MiB, up from 8 MiB)
* I/O
** {{arm|Generic Interrupt Controller}} (GIC) v3.0 (up from v2.0)
** 5.25x more PCIe lanes(42 lanes, up from 8)
*** 8 controllers (up from 1)
* Memory
** 2x memory channels (8 channels, up from 4)
*** 2x DIMMs (16 DIMMs, up from 8)
*** DDR4 (from DDR4)
*** Faster DDR rates (2666 MT/s, up from 1866 MT/s)
** 2.86x Higher bandwidth (170.7 GB/s, up from 59.73 GB/s)
* Package
** 3211-pin (up from 1624)

{{expand list}}

== Block Diagram ==
=== Entire SoC ===
:[[File:skylark block diagram.svg|800px]]

=== Memory Hierarchy ===
* Cache
** L1I Cache
*** 32 KiB
** L1D Cache
*** 32 KiB
** L2
*** 256 KiB
*** Shared per processor module
** L3
*** 32 MiB
*** ECC protected
*** Shared by entire chip
* System [[DRAM]]
** 8 channels
** 8 B/cycle/channel (@ memory clock)
** Up to DDR4 @ 2666 MT/s
** Up to 1 TiB
** ECC support, 

== Overview ==
{{empty section}}

== Bibliography ==
* AppliedMicro. (June, 2016). personal communication.
* Ampere Computing. (February 5, 2018). personal communication.
* Ampere Computing. (September 19, 2018). personal communication.
* David Schor. (September 19, 2018). "''[https://fuse.wikichip.org/news/1663/ampere-ships-first-gen-arm-server-processors/ Ampere Ships First Gen ARM Server Processors]''".
codename	Skylark +
core count	32 +
designer	AppliedMicro + and Ampere Computing +
first launched	2018 +
full page name	apm/microarchitectures/skylark +
instance of	microarchitecture +
instruction set architecture	ARMv8 +
manufacturer	TSMC +
microarchitecture type	CPU +
name	Skylark +
process	16 nm (0.016 μm, 1.6e-5 mm) +