From WikiChip
Editing amd/ryzen 7/3700u

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 13: Line 13:
 
|series=3000
 
|series=3000
 
|frequency=2,300 MHz
 
|frequency=2,300 MHz
−
|turbo frequency=4,000 MHz
+
|turbo frequency1=4,000 MHz
 
|bus type=PCIe 3.0
 
|bus type=PCIe 3.0
 
|clock multiplier=23
 
|clock multiplier=23
Line 30: Line 30:
 
|max memory=64 GiB
 
|max memory=64 GiB
 
|tdp=15 W
 
|tdp=15 W
−
|ctdp down=12 W
 
−
|ctdp up=35 W
 
 
|temp min=0° C
 
|temp min=0° C
 
|temp max=105 °C
 
|temp max=105 °C
 
|package name 1=amd,fp5
 
|package name 1=amd,fp5
 
}}
 
}}
−
'''Ryzen 7 3700U''' is a {{arch|64}} [[quad-core]] high-end performance [[x86]] mobile microprocessor introduced by [[AMD]] in early [[2019]]. This processor is based on AMD's {{amd|Zen+|Zen+ microarchitecture|l=arch}} and is fabricated on a [[12 nm process]]. The 3700U operates at a base frequency of 2.3 GHz with a [[TDP]] of 15 W and a {{amd|Precision Boost|Boost}} frequency of 4.0 GHz. This APU supports up to 32 GiB of dual-channel DDR4-2400 memory and incorporates {{amd|Radeon Vega 10}} Graphics operating at up to 1.4 GHz.
 
−
 
−
This model supports a configurable TDP-down of 12 W and TDP-up of 35 W.
 
−
 
−
 
−
== Cache ==
 
−
{{main|amd/microarchitectures/zen+#Memory_Hierarchy|l1=Zen+ § Cache}}
 
−
{{cache size
 
−
|l1 cache=384 KiB
 
−
|l1i cache=256 KiB
 
−
|l1i break=4x64 KiB
 
−
|l1i desc=4-way set associative
 
−
|l1d cache=128 KiB
 
−
|l1d break=4x32 KiB
 
−
|l1d desc=8-way set associative
 
−
|l1d policy=write-back
 
−
|l2 cache=2 MiB
 
−
|l2 break=4x512 KiB
 
−
|l2 desc=8-way set associative
 
−
|l2 policy=write-back
 
−
|l3 cache=4 MiB
 
−
|l3 break=1x4 MiB
 
−
}}
 
−
 
−
== Memory controller ==
 
−
{{memory controller
 
−
|type=DDR4-2400
 
−
|ecc=Yes
 
−
|max mem=32 GiB
 
−
|controllers=2
 
−
|channels=2
 
−
|max bandwidth=35.76 GiB/s
 
−
|bandwidth schan=17.88 GiB/s
 
−
|bandwidth dchan=35.76 GiB/s
 
−
}}
 
−
 
−
== Expansions ==
 
−
This processor has 12 PCIe lanes, 1x8 typically designated for a [[GPU]] and 4 additional lanes for storage (e.g., NVMe).
 
−
{{expansions main
 
−
|
 
−
{{expansions entry
 
−
|type=PCIe
 
−
|pcie revision=3.0
 
−
|pcie lanes=12
 
−
|pcie config=1x8+1x4
 
−
|pcie config 2=2x4+1x4
 
−
}}
 
−
}}
 
−
 
−
== Graphics ==
 
−
{{integrated graphics
 
−
| gpu                = Radeon Vega 10
 
−
| device id          =
 
−
| designer            = AMD
 
−
| execution units    = 10
 
−
| unified shaders    = 640
 
−
| max displays        = 4
 
−
| max memory          =
 
−
| frequency          =
 
−
| max frequency      = 1,400 MHz
 
−
 
−
| output crt          =
 
−
| output sdvo        =
 
−
| output dsi          =
 
−
| output edp          =
 
−
| output dp          = Yes
 
−
| output hdmi        = Yes
 
−
| output vga          =
 
−
| output dvi          =
 
−
 
−
| directx ver        = 12
 
−
| opengl ver        = 4.6
 
−
| opencl ver        = 2.2
 
−
| hdmi ver          =
 
−
| dp ver            =
 
−
| edp ver            =
 
−
| max res hdmi      =
 
−
| max res hdmi freq  =
 
−
| max res dp        =
 
−
| max res dp freq    =
 
−
| max res edp        =
 
−
| max res edp freq  =
 
−
| max res vga        =
 
−
| max res vga freq  =
 
−
}}
 
−
{{zen with vega hardware accelerated video table|col=1}}
 
−
 
−
== Features ==
 
−
{{x86 features
 
−
|real=Yes
 
−
|protected=Yes
 
−
|smm=Yes
 
−
|fpu=Yes
 
−
|x8616=Yes
 
−
|x8632=Yes
 
−
|x8664=Yes
 
−
|nx=Yes
 
−
|mmx=Yes
 
−
|emmx=Yes
 
−
|sse=Yes
 
−
|sse2=Yes
 
−
|sse3=Yes
 
−
|ssse3=Yes
 
−
|sse41=Yes
 
−
|sse42=Yes
 
−
|sse4a=Yes
 
−
|avx=Yes
 
−
|avx2=Yes
 
−
|avx512f=No
 
−
|avx512cd=No
 
−
|avx512er=No
 
−
|avx512pf=No
 
−
|avx512bw=No
 
−
|avx512dq=No
 
−
|avx512vl=No
 
−
|avx512ifma=No
 
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
−
|abm=Yes
 
−
|tbm=No
 
−
|bmi1=Yes
 
−
|bmi2=Yes
 
−
|fma3=Yes
 
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=Yes
 
−
|sha=Yes
 
−
|xop=No
 
−
|adx=Yes
 
−
|clmul=Yes
 
−
|f16c=Yes
 
−
|tbt1=No
 
−
|tbt2=No
 
−
|tbmt3=No
 
−
|bpt=No
 
−
|eist=No
 
−
|sst=No
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=No
 
−
|intelnodecontroller=No
 
−
|intelnode=No
 
−
|kpt=No
 
−
|ptt=No
 
−
|intelrunsure=No
 
−
|mbe=No
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=No
 
−
|tsx=No
 
−
|txt=No
 
−
|ht=No
 
−
|vpro=No
 
−
|vtx=No
 
−
|vtd=No
 
−
|ept=No
 
−
|mpx=No
 
−
|sgx=No
 
−
|securekey=No
 
−
|osguard=No
 
−
|intqat=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=Yes
 
−
|amdv=Yes
 
−
|amdsme=No
 
−
|amdtsme=No
 
−
|amdsev=No
 
−
|rvi=No
 
−
|smt=Yes
 
−
|sensemi=Yes
 
−
|xfr=No
 
−
|mxfr=No
 
−
|amdpb=No
 
−
|amdpb2=No
 
−
}}
 
−
 
−
== Die ==
 
−
{{further|amd/microarchitectures/zen+#Die|l1=Zen+ § Die}}
 
−
* [[14 nm process]]
 
−
* 4,940,000,000 transistors
 
−
* 209.78 mm² die size
 
−
 
−
 
−
: [[File:raven ridge die.png|650px]]
 
−
 
−
 
−
: [[File:raven ridge die (annotated).png|650px]]
 

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)

Templates used on this page:

Retrieved from "https://en.wikichip.org/wiki/amd/ryzen_7/3700u"
Facts about "Ryzen 7 3700U - AMD"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Ryzen 7 3700U - AMD#pcie +
base frequency2,300 MHz (2.3 GHz, 2,300,000 kHz) +
bus typePCIe 3.0 +
clock multiplier23 +
core count4 +
core namePicasso +
designerAMD +
die area209.78 mm² (0.325 in², 2.098 cm², 209,780,000 µm²) +
familyRyzen 7 +
first announcedJanuary 6, 2019 +
first launchedJanuary 6, 2019 +
full page nameamd/ryzen 7/3700u +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd sensemi technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension + and SenseMI Technology +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
integrated gpuRadeon Vega 10 +
integrated gpu designerAMD +
integrated gpu execution units10 +
integrated gpu max frequency1,400 MHz (1.4 GHz, 1,400,000 KHz) +
isax86-64 +
isa familyx86 +
l1$ size384 KiB (393,216 B, 0.375 MiB) +
l1d$ description8-way set associative +
l1d$ size128 KiB (131,072 B, 0.125 MiB) +
l1i$ description4-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size2 MiB (2,048 KiB, 2,097,152 B, 0.00195 GiB) +
l3$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
ldateJanuary 6, 2019 +
manufacturerGlobalFoundries +
market segmentMobile +
max cpu count1 +
max memory65,536 MiB (67,108,864 KiB, 68,719,476,736 B, 64 GiB, 0.0625 TiB) +
max memory bandwidth35.76 GiB/s (36,618.24 MiB/s, 38.397 GB/s, 38,397.008 MB/s, 0.0349 TiB/s, 0.0384 TB/s) +
max memory channels2 +
max operating temperature105 °C +
microarchitectureZen+ +
min operating temperature0° C +
model number3700U +
nameRyzen 7 3700U +
packageFP5 +
part numberYM3700C4T4MFG +
process12 nm (0.012 μm, 1.2e-5 mm) +
series3000 +
smp max ways1 +
supported memory typeDDR4-2400 +
tdp15 W (15,000 mW, 0.0201 hp, 0.015 kW) +
tdp down12 W (12,000 mW, 0.0161 hp, 0.012 kW) +
tdp up35 W (35,000 mW, 0.0469 hp, 0.035 kW) +
technologyCMOS +
thread count8 +
transistor count4,940,000,000 +
turbo frequency4,000 MHz (4 GHz, 4,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +