Editing amd/packages/socket am4

{{amd title|Socket AM4}}
{{package
|name=Socket AM4
|designer=AMD
|market=Desktop
|first launched=September 2016
|microarch=Zen
|tdp=105 W
|package name=OPGA-1331
|package type=Organic Micro Pin Grid Array
|package contacts=1331
|package dimension=40 mm
|package dimension 2=40 mm
|package pitch=1 mm
|socket name=Socket AM4
|socket type=PGA
}}
'''AM4''' is a socket for [[AMD]]'s mainstream series of microprocessors, serving as a successor to {{\\|Socket FM2+}} and {{\\|Socket AM3+}}.

== Overview ==
<!-- [[File:socket am4.svg|300px|right]] -->
Launching in September 2016, the '''AM4''' replaces a number of older AMD sockets including the {{\\|Socket FM2+}} and {{\\|Socket AM3+}} designed to unify all its mainstream processors from the low-end to the high-end in a single socket. At the time AMD stated the socket will feature prolong comparability life.

The AM4 accepts zero-insertion force '''µOPGA-1331'''-packaged microprocessors designed based on the {{amd|Excavator|l=arch}}, {{amd|Zen|l=arch}}, {{amd|Zen+|l=arch}}, {{amd|Zen 2|l=arch}}, and {{amd|Zen 3|l=arch}} microarchitectures, although the exact chips supported depends on the accompanying chipset.

== Chipsets ==
{{amd socket am4 chipsets}}

=== Support ===
AM4 socket support for a particular microprocessor depends on the chipset compatibility.

{| class="wikitable"
! colspan="8" | Socket AM4 Processor Support
|-
! rowspan="2" | Chipset !! colspan="2" | {{amd|Zen|l=arch}} !! colspan="2" | {{amd|Zen+|l=arch}} || colspan="2" | {{amd|Zen 2|l=arch}} || {{amd|Zen 3|l=arch}}
|-
| '''Summit Ridge''' || '''Raven Ridge'''|| '''Pinnacle Ridge''' || '''Picasso'''|| '''Matisse'''|| '''Renoir'''|| '''Vermeer'''
|-
| A320 || colspan="4" {{tchk|yes}} || colspan="3" {{tchk|no}}
|-
| A520 || colspan="5" {{tchk|no}} ||colspan="2" {{tchk|yes}}
|-
| B350 || colspan="4" {{tchk|yes}} || colspan="3" {{tchk|no}}
|-
| B450 || colspan="7" {{tchk|yes}}
|-
| B550 || colspan="5" {{tchk|no}} ||colspan="2" {{tchk|yes}}
|-
| X370 || colspan="4" {{tchk|yes}} || colspan="3" {{tchk|no}}
|-
| X470 || colspan="7" {{tchk|yes}}
|-
| X570 || colspan="2" {{tchk|no}} ||colspan="5" {{tchk|yes}}
|}

== Processors using Socket AM4 ==
<!-- NOTE: 
           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="19">List of all Socket AM4-based Processors</th></tr>
{{comp table header 1|cols=Price, Process, Launched, µarch, Family, Core, C, T, Freq, Turbo, TDP}}
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[socket::Socket AM4]]
 |?full page name
 |?model number
 |?release price
 |?process
 |?first launched
 |?microarchitecture
 |?microprocessor family
 |?core name
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |format=template
 |template=proc table 3
 |userparam=13
 |mainlabel=-
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[socket::Socket AM4]]}}
</table>
{{comp table end}}

== Socket Photographs ==
<gallery widths="400px" heights="400px">
File:socket mb am4.png|Socket AM4
</gallery>

== Package Diagram ==
:[[File:OPGA-1331 diag.svg]]

No data available. Approximate dimensions of the µOPGA-1331 package. All dimensions in millimeters.

== Socket Outline ==
:[[File:Socket AM4 FIT diag.svg]]

No data available. The diagram shows the dimensions of Foxconn Interconnect Technology Part No. PZ1331A-51ZZ*-1H. All dimensions in millimeters.

Socket drawing: https://www.fit-foxconn.com/Product/FileDownload?file=spec&path=%2FImages%2FProducts%2FSpec%2FPZ1331A-51ZZ0-1H_20181218103237.pdf&fileName=PZ1331A-51ZZ0-1H_20181218103237&fileType=pdf&fileClassID=2&productClass=Socket&productFamily=CPU%20Socket&productSeries=PGA%2FBGA&productNo=PZ1331A-51ZZ0-1H&version=7

== Pin Map ==
:[[File:OPGA-1331 pinmap.svg|800px]]

Note: it is unclear whether this diagram show socket top view, socket bottom view, CPU top view, or CPU bottom view.

=== Pin Description ===

{{work-in-progress}}

{| class="wikitable"
!Signal!!Description
|-
|48M_OSC||
|-
|AGPIO*||General Purpose I/O Pin
|-
|ALERT_L||
|-
|AM4R1||Socket identification
|-
|AZ_BITCLK||Azalia HD Audio Interface Bit Clock
|-
|AZ_RST_L||HD Audio Interface Reset
|-
|AZ_SDIN[2:0]||HD Audio Serial Data Inputs from Codec
|-
|AZ_SDOUT||HD Audio Serial Data Output to Codec
|-
|AZ_SYNC||HD Audio Sync signal to Codec
|-
|BLINK||
|-
|CLK_REQ[3:0]_L||
|-
|CLK_REQG_L||
|-
|CORETYPE[1:0]||Processor identification
|-
|DBREQ_L, DBRDY||Debug Request, Ready
|-
|DP[2:0]_AUXP/N||Display Port Auxiliary Channel Differential Pairs
|-
|DP[2:0]_HPD||Display Port Hot Plug Detect
|-
|DP[2:0]_TXP/N[3:0]||Display Port Differential Transmitter
|-
|DP_AUX_ZVSS||Compensation Resistor to VSS
|-
|DP_BLON||Display Panel Backlight Enable
|-
|DP_DIGON||Display Panel Power Enable
|-
|DP_STEREOSYNC||VESA Stereo Sync
|-
|DP_VARY_BL||Display Backlight Brightness Control
|-
|DP_ZVSS||Compensation Resistor to VSS
|-
|EGPIO*||General Purpose I/O Pin
|-
|ESPI_ALERT_L||
|-
|ESPI_CLK||ESPI Clock
|-
|ESPI_CS_L||ESPI Chip Select
|-
|ESPI_DAT[3:0]||ESPI Data
|-
|ESPI_RESET_L||
|-
|FANIN0||
|-
|FANOUT0||
|-
|GENINT1/2_L||
|-
|GFX_CLKP/N||GFX Differential Reference Clock
|-
|GPP_CLK[3:0]P/N||GPP Lane 3:0 Differential Reference Clock
|-
|I2C[3:2]_SCL/SDA||I2C Bus Clock, Data
|-
|LAD[3:0]||Low Pin Count Interface Command/Address/Data
|-
|KBRST_L||
|-
|LDRQ0_L||
|-
|LFRAME_L||LPC Bus Frame
|-
|LPCCLK[1:0]||LPC 33 MHz Clock
|-
|LPC_CLKRUN_L||LPC CLKRUN Signal
|-
|LPC_PD_L||LPC Power Down
|-
|LPC_PME_L||LPC PME Signal
|-
|LPC_RST_L||LPC Reset
|-
|MA/B[1:0]_CKE[1:0]||DRAM Clock Enable
|-
|MA/B[1:0]_CS_L[1:0]||DRAM Chip Select
|-
|MA/B[1:0]_ODT[1:0]||DRAM Enable Pins for On Die Termination
|-
|MA/B_ACT_L||DRAM Activation Command
|-
|MA/B_ADD[13:0]||DRAM Column/Row Address
|-
|MA/B_ADD_17||DRAM Address Bit A17 (16 GBit DRAMs)
|-
|MA/B_ALERT_L||DRAM CRC or Parity Error
|-
|MA/B_BANK[1:0]||DRAM Bank Address
|-
|MA/B_BG[1:0]||DRAM Bank Group
|-
|MA/B_CAS_L_ADD15||DRAM Column Address Strobe or Address A15
|-
|MA/B_CHECK[7:0]||DRAM ECC Bits
|-
|MA/B_CLK_L/H[3:0]||DRAM Differential Clock
|-
|MA/B_DATA[63:0]||DRAM Data Bus
|-
|MA/B_DM[8:0]||DRAM Data Mask
|-
|MA/B_DQS_L/H[8:0]||DRAM Differential Data Strobe
|-
|MA/B_EVENT_L||DRAM Thermal Event Status
|-
|MA/B_PAROUT||DRAM Command/Address Parity
|-
|MA/B_RAS_L_ADD16||DRAM Row Address Strobe or Address A16
|-
|MA/B_RESET_L||DRAM Reset Pin for Suspend-to-RAM Power Management Mode
|-
|MA/B_WE_L_ADD14||DRAM Write Enable or Address A14
|-
|MA/B_ZVDDIO_MEM_S3||
|-
|MA/B_ZVSS||Compensation Resistor to VSS
|-
|OSCIN||
|-
|P0A_ZVSS||Compensation Resistor to VSS
|-
|P0B_ZVSS||Compensation Resistor to VSS
|-
|PCIE_RST_L||PCIe Reset
|-
|PROCHOT_L||Processor in HTC-active state
|-
|PWROK||Voltages and clocks have reached specified operation
|-
|PWR_BTN_L||
|-
|PWR_GOOD||
|-
|P_GFX_TX/RXP/N[15:0]||GFX PCIe Transmit/Receive Data Differential Pairs
|-
|P_GPP_TX/RXP/N[3:0]||General Purpose PCIe Transmit/Receive Data Differential Pairs
|-
|SATA_IS[1:0]_L||
|-
|SATA_TX/RX[1:0]P/N||SATA Transmit/Receive Data Differential Pairs
|-
|SATA_ZP[1:0]_L||
|-
|P_HUB_TX/RXP/N[3:0]||Hub PCIe Transmit/Receive Data Differential Pairs
|-
|P_ZVDDP||
|-
|P_ZVSS||Compensation Resistor to VSS
|-
|RESET_L||Processor Reset
|-
|RSMRST_L||Resume Reset, VSB power on reset for South Bridge
|-
|RSVD||Reserved
|-
|RTCCLK||32 kHz input for RTC
|-
|S0A3_GPIO||
|-
|S5_MUX_CTRL||
|-
|SATA_ACT_L||SATA Channel Active
|-
|SATA_ZVDDP||
|-
|SATA_ZVSS||Compensation Resistor to VSS
|-
|SCL[1:0], SDA[1:0]||SMBus Clock, Data
|-
|SERIRQ||LPC SERIRQ Signal
|-
|SGPIO0_CLK||
|-
|SIC, SID||Sideband Temperature Sensor Interface Clock, Data
|-
|SLP_S3_L||
|-
|SLP_S5_L||
|-
|SPI_CLK||SPI Clock
|-
|SPI_CS1/2_L||SPI Chip Select
|-
|SPI_DI/DO||SPI Data Input/Output
|-
|SPI_HOLD_L||
|-
|SPI_TPM_CS_L||
|-
|SPI_WP_L||SPI Write Protect
|-
|SPKR||
|-
|SVC, SVD||Serial VID Interface Clock, Data
|-
|SVT||
|-
|SYS_RESET_L||System Reset
|-
|TCK, TDI, TDO, TMS, TRST_L||JTAG Interface
|-
|TEST*||Test Signals
|-
|THERMTRIP_L||Thermal Sensor Trip Output
|-
|USB[3:0]_ZVSS||Compensation Resistor to VSS
|-
|USB_HSD[3:0]P/N||USB High Speed Data Differential Pairs
|-
|USB_OC[3:0]_L||USB Over Current
|-
|USB_SS_[3:0]TX/RXP/N||USB Super Speed Transmit/Receive Differential Pairs
|-
|USB_SS_ZVDDP||
|-
|USB_SS_ZVSS||Compensation Resistor to VSS
|-
|USB_ZVSS||Compensation Resistor to VSS
|-
|VDDBT_RTC_G||
|-
|VDDCR_CPU||Core Power Supply
|-
|VDDCR_CPU_SENSE||VDDCR_CPU Voltage Monitor Pin
|-
|VDDCR_SOC||SOC Power Supply
|-
|VDDCR_SOC_S5||
|-
|VDDCR_SOC_SENSE||VDDCR_SOC Voltage Monitor Pin
|-
|VDDIO_AUDIO||
|-
|VDDIO_MEM_S3||DRAM I/O Ring Power Supply
|-
|VDDIO_MEM_S3_SENSE||VDDIO_MEM_S3 Voltage Monitor Pin
|-
|VDDP||<!-- Filtered PLL Power Supply? -->
|-
|VDDP_S5||
|-
|VDDP_SENSE||VDDP Voltage Monitor Pin
|-
|VDD_18||1.8V SOC Power Supply
|-
|VDD_18_S5||
|-
|VDD_33||3.3V SOC Power Supply
|-
|VDD_33_S5||
|-
|VSS||Ground
|-
|VSS_SENSE_A/B||
|-
|WAKE_L||PCIe WAKE Signal
|-
|X32K_X1/2||RTC Crystal Oscillator
|-
|X48M_X1/2||
|}

== See also ==
* {{\\|Socket AM3+}}
* {{\\|Socket FM2+}}
* {{\\|Socket SP3}}
* {{\\|Socket TR4}}
* {{\\|Socket TRX4}}

[[Category:amd]]
designer	AMD +
first launched	September 2016 +
instance of	package +
market segment	Desktop +
microarchitecture	Zen +
name	Socket AM4 +
package	OPGA-1331 +
package contacts	1,331 +
package length	40 mm (4 cm, 1.575 in) +
package pitch	1 mm (0.0394 in) +
package type	Organic Micro Pin Grid Array +
package width	40 mm (4 cm, 1.575 in) +
socket	Socket AM4 +
tdp	105 W (105,000 mW, 0.141 hp, 0.105 kW) +