Editing amd/microarchitectures/k6

{{amd title|K6|arch}}
{{microarchitecture
| atype            = CPU
| name             = K6
| designer         = AMD
| designer 2       = NexGen
| manufacturer     = AMD
| introduction     = April 2, 1997
| phase-out        = 2000
| process          = 350 nm
| process 2        = 250 nm
|isa=x86-32

| succession       = Yes
| predecessor      = K5
| predecessor link = amd/microarchitectures/k5
| successor        = K6-2
| successor link   = amd/microarchitectures/k6-2
}}
'''K6''' was the [[microarchitecture]] for [[AMD]]'s {{amd|K6}} line of microprocessors as a successor to the {{\\|K5}}. Contrary to its namesake, K6 design is entirely [[NexGen]]'s and not based on {{\\|K5}}. Launched in early [[1997]], the K6 microarchitecture provided the superior performance AMD needed to become a viable competitor to Intel (performance {{\\|K5}} failed to deliver). K6 was superseded by {{\\|K6-2}} in 1998.

== Architecture ==
{{empty section}}

== Die Shot ==
{{empty section}}

== All K6 Chips ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
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           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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<table class="wikitable sortable">
<tr><th colspan="6" style="background:#D6D6FF;">K6 Chips</th></tr>
<tr><th>Model</th><th>Core</th><th>Launched</th><th>Power Dissipation</th><th>Freq</th><th>Max Mem</th></tr>
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::K6]]
 |?full page name
 |?model number
 |?core name
 |?first launched
 |?power dissipation#W
 |?base frequency#MHz
 |?max memory#GB
 |format=template
 |template=proc table 2
 |searchlabel=
 |userparam=7
 |mainlabel=-
}}
{{table count|col=6|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::K6]]}}
</table>

== See also ==
* {{amd|K6}}
* {{intel|P6}}
@@ Line 21: / Line 21: @@
 == Architecture ==
-* 6-7 stage integer pipeline
+{{empty section}}
-** Fetch
-** Decode
-** Micro-op issue
-** Operand Fetch
-** Execute 1
-** Optional Execute 2
-** Commit
-* Branch Predictor
-** 2-level predictor with 8192 entry branch history table
-*** Does not store target addresses. Target addresses are calculated during instruction decode
-** 16-entry branch target cache
-*** Caches 16 bytes of instructions at the branch target, and supplies that directly to the decoders to avoid a 1-cycle penalty
-** 16-entry return address stack
-* 32K 2-way L1 Instruction Cache
-** Also holds 20K of predecode data. Instructions are predecoded as L1 instruction cache is filled
-** 64 entry TLB
-* Fetch and Decode
-** 16 instruction bytes fetched per cycle, either from L1 instruction cache or branch target cache
-** Decoders can handle the following combinations per clock:
-*** Short decode: Two x86 instructions that generate up to two micro-ops each
-*** Vector decode: One x86 instruction that generates up to four micro-ops
-*** Complex instructions handled by microcode
-* Out of order execution resources
-** Scheduler holds 6 groups of 4 micro-ops, or up to 12 x64 instructions
-*** Receives a group of 4 micro-ops from decoders every cycle. If fewer than 4 micro-ops are generated from the decoders, empty slots are padded with NOPs
-*** Retires one 4-micro-op group every cycle
-** 48 integer registers: 8 architectural, 16 scratch, 24 rename
-** 21 MMX registers: 8 architectural, 1 scratch, 12 rename
-** Up to 7 outstanding branches
-** 7 entry store queue
-* Issues up to 6 micro-ops per cycle. Ports:
-** Integer X: All ALU ops, including multiplies and divides
-** Integer Y: Basic ALU ops
-*** Both integer pipelines can handle MMX/3DNow instructions, but share MMX/3DNow multiplier and MMX shifter functional units. If the two pipelines try to issue operations to a shared functional unit, one operation will stall.
-** Floating point
-** Load
-** Store
-** Branch
-* 32K 2-way L1 Data Cache
-** Dual ported, write back
-** 128 entry TLB
-** Load unit has 2-cycle latency
-[[File:K6 block diagram.png]]
 == Die Shot ==
@@ Line 100: / Line 57: @@
 * {{amd|K6}}
 * {{intel|P6}}
-== References ==
-* AMD K6-2 Data Sheet [http://www.amd-k6.com/wp-content/uploads/2012/07/AMD_K6-2_Desktop_Datasheet.pdf]
-* AMD K6 Code Optimization [http://www.ii.uib.no/~osvik/amd_opt/21924d.pdf]
codename	K6 +
designer	AMD + and NexGen +
first launched	April 2, 1997 +
full page name	amd/microarchitectures/k6 +
instance of	microarchitecture +
instruction set architecture	x86-32 +
manufacturer	AMD +
microarchitecture type	CPU +
name	K6 +
phase-out	2000 +
process	350 nm (0.35 μm, 3.5e-4 mm) + and 250 nm (0.25 μm, 2.5e-4 mm) +