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{{amd title|AMD-K6-IIIE+/450ACR}} | {{amd title|AMD-K6-IIIE+/450ACR}} | ||
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| name = AMD-K6-IIIE+/450ACR | | name = AMD-K6-IIIE+/450ACR | ||
| no image = Yes | | no image = Yes | ||
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| model number = AMD-K6-IIIE+/450ACR | | model number = AMD-K6-IIIE+/450ACR | ||
| part number = AMD-K6-IIIE+/450ACR | | part number = AMD-K6-IIIE+/450ACR | ||
| − | |||
| part number 2 = | | part number 2 = | ||
| part number 3 = | | part number 3 = | ||
| + | | part number 4 = | ||
| market = Embedded | | market = Embedded | ||
| first announced = September 25, 2000 | | first announced = September 25, 2000 | ||
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| thread count = 1 | | thread count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 4 | + | | max memory = 4 GiB |
| + | |||
| − | |||
| power = | | power = | ||
| v core = 2.0 V | | v core = 2.0 V | ||
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}} | }} | ||
'''AMD-K6-IIIE+/450ACR''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 450 MHz with a bus of 100 MHz and a multiplier of 4.5. This chip had a TDP of 12 W. | '''AMD-K6-IIIE+/450ACR''' is a {{arch|32}} [[x86]] embedded microprocessor designed by [[AMD]] and introduced in late [[2000]]. This MPU which was manufactured on a [[0.18 µm process]], based on {{amd|microarchitectures/k6-iii|K6-III microarchitecture}}, operated at 450 MHz with a bus of 100 MHz and a multiplier of 4.5. This chip had a TDP of 12 W. | ||
| + | |||
| + | == Cache == | ||
| + | {{main|amd/microarchitectures/k6-iii#Memory_Hierarchy|l1=K6-III § Cache}} | ||
| + | [[L3$]] can be 512 KiB to 2 MiB, depending on manufacturer and [[motherboard]] model. L3$ is off-chip. | ||
| + | {{cache info | ||
| + | |l1i cache=32 KiB | ||
| + | |l1i break=1x32 KiB | ||
| + | |l1i desc=2-way set associative | ||
| + | |l1i extra= | ||
| + | |l1d cache=32 KiB | ||
| + | |l1d break=1x32 KiB | ||
| + | |l1d desc=2-way set associative | ||
| + | |l1d extra= | ||
| + | |l2 cache=256 KiB | ||
| + | |l2 break=1x256 KiB | ||
| + | |l2 desc=4-way set associative | ||
| + | |l2 extra=(shared) | ||
| + | |l3 cache= | ||
| + | |l3 break= | ||
| + | |l3 desc= | ||
| + | |l3 extra= | ||
| + | }} | ||
| + | |||
| + | == Graphics == | ||
| + | This processors has no integrated graphics processing unit. | ||
| + | |||
| + | == Features == | ||
| + | {{x86 features | ||
| + | | mmx = Yes | ||
| + | | emmx = Yes | ||
| + | | 3dnow = Yes | ||
| + | | e3dnow = Yes | ||
| + | | pownow = Yes | ||
| + | }} | ||
| + | * Auto-power down state | ||
| + | * Stop clock state | ||
| + | * Halt state | ||
Latest revision as of 16:09, 13 December 2017
| Edit Values | |
| AMD-K6-IIIE+/450ACR | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | AMD-K6-IIIE+/450ACR |
| Part Number | AMD-K6-IIIE+/450ACR |
| Market | Embedded |
| Introduction | September 25, 2000 (announced) September 25, 2000 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | K6-III+ |
| Series | K6-III+ Embedded |
| Frequency | 449.99 MHz |
| Bus type | FSB |
| Bus speed | 99.99 MHz |
| Bus rate | 99.99 MT/s |
| Clock multiplier | 4.5 |
| CPUID | 5D0 |
| Microarchitecture | |
| Microarchitecture | K6-III |
| Platform | Super 7 |
| Core Family | 5 |
| Core Model | 13 |
| Core Stepping | 0, 1, 2, 3 |
| Process | 0.18 µm |
| Transistors | 21,400,000 |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Threads | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 2.0 V ± 0.1 V |
| VI/O | 3.3675 V ± 7% |
| TDP | 12 W |
| Tcase | 0 °C – 70 °C |
| Tstorage | -65 °C – 150 °C |
AMD-K6-IIIE+/450ACR is a 32-bit x86 embedded microprocessor designed by AMD and introduced in late 2000. This MPU which was manufactured on a 0.18 µm process, based on K6-III microarchitecture, operated at 450 MHz with a bus of 100 MHz and a multiplier of 4.5. This chip had a TDP of 12 W.
Cache[edit]
- Main article: K6-III § Cache
L3$ can be 512 KiB to 2 MiB, depending on manufacturer and motherboard model. L3$ is off-chip.
| Cache Info [Edit Values] | ||
| L1I$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L1D$ | 32 KiB 32,768 B 0.0313 MiB |
1x32 KiB 2-way set associative |
| L2$ | 256 KiB 0.25 MiB 262,144 B 2.441406e-4 GiB |
1x256 KiB 4-way set associative (shared) |
Graphics[edit]
This processors has no integrated graphics processing unit.
Features[edit]
[Edit/Modify Supported Features]
 |
Supported x86 Extensions & Processor Features
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- Auto-power down state
- Stop clock state
- Halt state
Facts about "AMD-K6-IIIE+/450ACR - AMD"
| l1d$ description | 2-way set associative + |
| l1i$ description | 2-way set associative + |
| l2$ description | 4-way set associative + |
