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Difference between revisions of "amd/k6-2/k6-2-300bnz-66"
< amd‎ | k6-2

Line 47: Line 47:
  
 
| electrical          = Yes
 
| electrical          = Yes
| power              =  
+
| power              = 10 W
 
| v core              = 1.8 V
 
| v core              = 1.8 V
 
| v core tolerance    = 0.1 V
 
| v core tolerance    = 0.1 V

Revision as of 05:53, 5 August 2016

Template:mpu K6-2/300BNZ-66 was a 32-bit x86 K6-2-based mobile microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 300 MHz with a FSB operating at 66 MHz.

Cache

Main article: K6-2 § Cache

L2$ can be 512 KB to 1 MB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative
L1D$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state

Documents

DataSheet

l1d$ description2-way set associative +
l1i$ description2-way set associative +