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== Overview == | == Overview == | ||
− | K5 was a result of desperation and frustration with cloning and second-sourcing [[Intel]]-based [[x86]] microprocessors. Rumors for the development of K5 dates back to mid-[[1993]], however it was only officially announced in late [[1994]] with the goal of releasing the first batch of chips in in [[1995]]. K5, which stands for [[wikipedia:Kryptonite|Kryptonite]] 5, which as its name implied was an ambitious attempt by AMD to take on Intel (being [[wikipedia:Superman|Superman]], metaphorically). The design suffered significant delays first due to early design problems and later due to problems with various [[x86]] incompatibilities. The first few models | + | K5 was a result of desperation and frustration with cloning and second-sourcing [[Intel]]-based [[x86]] microprocessors. Rumors for the development of K5 dates back to mid-[[1993]], however it was only officially announced in late [[1994]] with the goal of releasing the first batch of chips in in [[1995]]. K5, which stands for [[wikipedia:Kryptonite|Kryptonite]] 5, which as its name implied was an ambitious attempt by AMD to take on Intel (being [[wikipedia:Superman|Superman]], metaphorically). The design suffered significant delays first due to early design problems and later due to problems with various [[x86]] incompatibilities. The first few models were finally released in March of [[1996]]. |
The first version of {{amd|microarchitectures/k5|K5 Microarchitecture}} introduced, '''SSA/5''', had many technical improvements over Intel's {{intel|Pentium}}, making it well ahead of its time. It had an instruction translator that converted [[CISC]] instructions into simpler [[RISC]] instructions. Due to numerous manufacturing issues and design choices, K5 failed to deliver the expected performance it should have. | The first version of {{amd|microarchitectures/k5|K5 Microarchitecture}} introduced, '''SSA/5''', had many technical improvements over Intel's {{intel|Pentium}}, making it well ahead of its time. It had an instruction translator that converted [[CISC]] instructions into simpler [[RISC]] instructions. Due to numerous manufacturing issues and design choices, K5 failed to deliver the expected performance it should have. | ||
AMD went back and readdressed some of the deficiencies the SSA/5 design had. AMD introduced the new version of K5, named '''5k86''', in October of 1996. AMD had reworked the way memory gets accessed and flows through, from [[L1$]] to [[L2$]] and main. The results is upward of 35% performance improvements across the board. 5k86's performance outmatched Pentium's with lower clock speed. | AMD went back and readdressed some of the deficiencies the SSA/5 design had. AMD introduced the new version of K5, named '''5k86''', in October of 1996. AMD had reworked the way memory gets accessed and flows through, from [[L1$]] to [[L2$]] and main. The results is upward of 35% performance improvements across the board. 5k86's performance outmatched Pentium's with lower clock speed. | ||
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== Architecture == | == Architecture == | ||
{{main|amd/microarchitectures/k5|l1=K5 Microarchitecture}} | {{main|amd/microarchitectures/k5|l1=K5 Microarchitecture}} | ||
{{empty section}} | {{empty section}} | ||
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== Die Shot == | == Die Shot == | ||
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{{table count|col=11|ask=[[Category:microprocessor models by amd]][[instance of::microprocessor]][[microprocessor family::K5]][[core name::5k86]]}} | {{table count|col=11|ask=[[Category:microprocessor models by amd]][[instance of::microprocessor]][[microprocessor family::K5]][[core name::5k86]]}} | ||
</table> | </table> | ||
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Facts about "K5 - AMD"
designer | AMD + |
first announced | October 24, 1994 + |
first launched | March 27, 1996 + |
full page name | amd/k5 + |
instance of | microprocessor family + |
instruction set architecture | IA-32 + |
main designer | AMD + |
manufacturer | AMD + |
microarchitecture | K5 + |
name | AMD K5 + |
package | SPGA-296 + |
process | 500 nm (0.5 μm, 5.0e-4 mm) + and 350 nm (0.35 μm, 3.5e-4 mm) + |
socket | Socket 5 + and Socket 7 + |
technology | CMOS + |
word size | 32 bit (4 octets, 8 nibbles) + |