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Latest revision Your text
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|model number=7252
 
|model number=7252
 
|part number=100-000000080
 
|part number=100-000000080
−
|part number 2=100-100000080WOF
 
 
|market=Server
 
|market=Server
 
|first announced=August 7, 2019
 
|first announced=August 7, 2019
 
|first launched=August 7, 2019
 
|first launched=August 7, 2019
−
|release price=$475.00
 
 
|family=EPYC
 
|family=EPYC
 
|series=7002
 
|series=7002
 
|locked=Yes
 
|locked=Yes
−
|frequency=3,100 MHz
+
|frequency=2,800 MHz
 
|turbo frequency=3,200 MHz
 
|turbo frequency=3,200 MHz
−
|clock multiplier=31
+
|clock multiplier=28
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
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|core name=Rome
 
|core name=Rome
 
|core family=23
 
|core family=23
−
|core model=49
 
−
|core stepping=B0
 
 
|process=7 nm
 
|process=7 nm
 
|process 2=14 nm
 
|process 2=14 nm
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|core count=8
 
|core count=8
 
|thread count=16
 
|thread count=16
 +
|max cpus=2
 
|max memory=4 TiB
 
|max memory=4 TiB
−
|max cpus=2
 
 
|tdp=120 W
 
|tdp=120 W
 
|package name 1=amd,socket_sp3
 
|package name 1=amd,socket_sp3
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|predecessor link=amd/epyc/7251
 
|predecessor link=amd/epyc/7251
 
}}
 
}}
−
'''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on a [[GlobalFoundries]] [[14 nm process]]. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of memory per socket.
+
'''EPYC 7252''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7252 has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of eight channels DDR4-3200 memory per socket.
  
 
== Cache ==
 
== Cache ==
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|l1d break=8x32 KiB
 
|l1d break=8x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
−
|l1d policy=write-back
 
 
|l2 cache=4 MiB
 
|l2 cache=4 MiB
 
|l2 break=8x512 KiB
 
|l2 break=8x512 KiB
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== Memory controller ==
 
== Memory controller ==
−
This model supports up to 8 channels of up to DDR4-3200 memory<ref name="specs">[https://www.amd.com/en/products/cpu/amd-epyc-7252 "AMD EPYC™ 7252"]. <i>AMD.com</i>. Retrieved October 2020.</ref><ref name="datasheet">[https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020</ref> with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the [[amd/infinity_fabric|IFOP]] links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK<ref name="isscc2020j-chiplet">Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:[https://doi.org/10.1109/ISSCC19947.2020.9063103 10.1109/ISSCC19947.2020.9063103]</ref>). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).<ref name="datasheet"/>
+
In a dual-socket configuration, the maximum supported memory doubles to 8 TiB along with the maximum theoretical bandwidth of 381.5 GiB/s for the entire system.
  
 
{{memory controller
 
{{memory controller
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|bandwidth ochan=190.7 GiB/s
 
|bandwidth ochan=190.7 GiB/s
 
}}
 
}}
−
 
−
== Expansions ==
 
−
{{expansions main
 
−
|
 
−
{{expansions entry
 
−
|type=PCIe
 
−
|pcie revision=4.0
 
−
|pcie lanes=128
 
−
|pcie config=x16
 
−
|pcie config 2=x8
 
−
}}
 
−
}}
 
−
 
−
== Features ==
 
−
{{x86 features
 
−
|real=Yes
 
−
|protected=Yes
 
−
|smm=Yes
 
−
|fpu=Yes
 
−
|x8616=Yes
 
−
|x8632=Yes
 
−
|x8664=Yes
 
−
|nx=Yes
 
−
|mmx=Yes
 
−
|emmx=Yes
 
−
|sse=Yes
 
−
|sse2=Yes
 
−
|sse3=Yes
 
−
|ssse3=Yes
 
−
|sse41=Yes
 
−
|sse42=Yes
 
−
|sse4a=Yes
 
−
|sse_gfni=No
 
−
|avx=Yes
 
−
|avx_gfni=No
 
−
|avx2=Yes
 
−
|avx512f=No
 
−
|avx512cd=No
 
−
|avx512er=No
 
−
|avx512pf=No
 
−
|avx512bw=No
 
−
|avx512dq=No
 
−
|avx512vl=No
 
−
|avx512ifma=No
 
−
|avx512vbmi=No
 
−
|avx5124fmaps=No
 
−
|avx512vnni=No
 
−
|avx5124vnniw=No
 
−
|avx512vpopcntdq=No
 
−
|avx512gfni=No
 
−
|avx512vaes=No
 
−
|avx512vbmi2=No
 
−
|avx512bitalg=No
 
−
|avx512vpclmulqdq=No
 
−
|abm=Yes
 
−
|tbm=No
 
−
|bmi1=Yes
 
−
|bmi2=Yes
 
−
|fma3=Yes
 
−
|fma4=No
 
−
|aes=Yes
 
−
|rdrand=Yes
 
−
|sha=Yes
 
−
|xop=No
 
−
|adx=Yes
 
−
|clmul=Yes
 
−
|f16c=Yes
 
−
|bfloat16=No
 
−
|tbt1=No
 
−
|tbt2=No
 
−
|tbmt3=No
 
−
|tvb=No
 
−
|bpt=No
 
−
|eist=No
 
−
|sst=No
 
−
|flex=No
 
−
|fastmem=No
 
−
|ivmd=No
 
−
|intelnodecontroller=No
 
−
|intelnode=No
 
−
|kpt=No
 
−
|ptt=No
 
−
|intelrunsure=No
 
−
|mbe=No
 
−
|isrt=No
 
−
|sba=No
 
−
|mwt=No
 
−
|sipp=No
 
−
|att=No
 
−
|ipt=No
 
−
|tsx=No
 
−
|txt=No
 
−
|ht=No
 
−
|vpro=No
 
−
|vtx=No
 
−
|vtd=No
 
−
|ept=No
 
−
|mpx=No
 
−
|sgx=No
 
−
|securekey=No
 
−
|osguard=No
 
−
|intqat=No
 
−
|dlboost=No
 
−
|3dnow=No
 
−
|e3dnow=No
 
−
|smartmp=No
 
−
|powernow=No
 
−
|amdvi=Yes
 
−
|amdv=Yes
 
−
|amdsme=Yes
 
−
|amdtsme=Yes
 
−
|amdsev=Yes
 
−
|rvi=No
 
−
|smt=Yes
 
−
|sensemi=Yes
 
−
|xfr=No
 
−
|xfr2=No
 
−
|mxfr=No
 
−
|amdpb=No
 
−
|amdpb2=Yes
 
−
|amdpbod=No
 
−
}}
 
−
 
−
== References ==
 
−
<references/>
 

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Facts about "EPYC 7252 - AMD"
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EPYC 7252 - AMD#pcie +
base frequency3,100 MHz (3.1 GHz, 3,100,000 kHz) +
clock multiplier31 +
core count8 +
core family23 +
core model49 +
core nameRome +
core steppingB0 +
designerAMD +
die count3 +
familyEPYC +
first announcedAugust 7, 2019 +
first launchedAugust 7, 2019 +
full page nameamd/epyc/7252 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd precision boost 2true +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size64 MiB (65,536 KiB, 67,108,864 B, 0.0625 GiB) +
ldateAugust 7, 2019 +
manufacturerTSMC + and GlobalFoundries +
market segmentServer +
max cpu count2 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels8 +
microarchitectureZen 2 +
model number7252 +
nameEPYC 7252 +
packageFCLGA-4094 + and SP3 +
part number100-000000080 + and 100-100000080WOF +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 475.00 (€ 427.50, £ 384.75, ¥ 49,081.75) +
series7002 +
smp max ways2 +
socketLGA-4094 + and SP3 +
supported memory typeDDR4-3200 +
tdp120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technologyCMOS +
thread count16 +
turbo frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +