From WikiChip
Editing amd/epyc
Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.
The edit can be undone.
Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.
This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.
Latest revision | Your text | ||
Line 99: | Line 99: | ||
* All models support everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | * All models support everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | ||
− | Additionally, all models support AMD's new {{amd|Secure Memory Encryption}} (SME) | + | Additionally, all models support AMD's new {{amd|Secure Memory Encryption}} (SME) and {{amd|Secure Encrypted Virtualization}} (SEV) security technologies. |
It should be noted that for some models, there are two [[TDP]] values given because the TDP will depend on the memory rate used for the system (i.e., either 2666 MT/s or 2400 MT/s). The ''All Boost'' frequency is the {{amd|precision boost}} frequency that can be applied to all cores when they're all active. When less than 12 cores are active, however, the ''Max Boost'' frequency can be applied for even higher performance - provided there's sufficient thermal and electrical headroom. | It should be noted that for some models, there are two [[TDP]] values given because the TDP will depend on the memory rate used for the system (i.e., either 2666 MT/s or 2400 MT/s). The ''All Boost'' frequency is the {{amd|precision boost}} frequency that can be applied to all cores when they're all active. When less than 12 cores are active, however, the ''Max Boost'' frequency can be applied for even higher performance - provided there's sufficient thermal and electrical headroom. |
Facts about "EPYC - AMD"
designer | AMD + |
first announced | May 16, 2017 + |
first launched | June 20, 2017 + |
full page name | amd/epyc + |
instance of | system on a chip family + |
instruction set architecture | x86-64 + |
main designer | AMD + |
manufacturer | GlobalFoundries + and TSMC + |
microarchitecture | Zen +, Zen 2 +, Zen 3 + and Zen 4 + |
name | AMD EPYC + |
package | FCLGA-4094 + and FCLGA-? + |
process | 14 nm (0.014 μm, 1.4e-5 mm) +, 7 nm (0.007 μm, 7.0e-6 mm) + and 5 nm (0.005 μm, 5.0e-6 mm) + |
socket | Socket SP3 + and Socket SP5 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |