Editing amd/cores/naples

{{amd title|Naples|core}}
{{core
|name=Naples
|image=amd naples (front).png
|caption=Back
|back image=amd naples (back).png
|caption=Back
|developer=AMD
|manufacturer=GlobalFoundries
|first announced=March 7, 2017
|first launched=June 20, 2017
|isa=x86-64
|microarch=Zen
|word=64 bit
|proc=14 nm
|tech=CMOS
|clock min=2,000 MHz
|clock max=2,400 MHz
|package name 1=amd,socket_sp3
|successor=Rome
|successor link=amd/cores/rome
}}
'''Naples''' is codename for [[AMD]]'s highest-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen|l=arch}} microarchitecture. Naples processors support up [[32 cores]] and are fabricated on GlobalFoundries' [[14 nm process]]. Naples-based processors are branded as {{amd|EPYC}}.

== Overview ==
[[File:amd naples 2 sock.jpg|right|thumb]]
AMD Naples [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen|l=arch}} microarchitecture. Naples SoCs support both single and 2-way multiprocessing with up to a maximum of 32 cores (and 64 threads) per processor for a total of up to 64 cores (and 128 threads) for a 2-way MP system. Those SoCs sports 128 PCIe lanes each, however, half of them are lost when in 2-way MP (leaving the system with the same overall lanes count as a single socket solution). Communication between the two chips is done via AMD's {{amd|Infinity Fabric}} protocol over the 64 reserved lanes.

=== Common Features ===
All Naples processors have the following:
* 128 PCIe lanes (in both single-way and dual-way multiprocessing)
* Octa-channel Memory
** Up to DDR4-2666 ECC
** Up to 2 [[TiB]] (4 TiB in 2MP)
* Up to 32 cores / 64 threads
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}

== Naples Processors ==
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           This table is generated automatically from the data in the actual articles.
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           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc5 tc6">
{{comp table header|main|10:List of Naples Processors}}
{{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
{{#ask: [[Category:microprocessor models by amd]] [[core name::Naples]]
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?tdp
 |?l2$ size
 |?l3$ size
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |format=template
 |template=proc table 3
 |userparam=12
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Naples]]}}
</table>
{{comp table end}}

== See also ==
{{amd zen core see also}}
* {{intel|Skylake|l=arch}}
** {{intel|Skylake SP|l=core}}
back image	+
designer	AMD +
first announced	March 7, 2017 +
first launched	June 20, 2017 +
instance of	core +
isa	x86-64 +
main image	+
main image caption	Package, front +
manufacturer	GlobalFoundries +
microarchitecture	Zen +
name	Naples +
package	FCLGA-4094 + and SP3 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	LGA-4094 + and SP3 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +