Editing amd/cores/naples

{{amd title|Naples|core}}
{{core
| name              = Naples
| image             = amd naples.png
| image size        = 
| image 2           = 
| image 2 size      = 
| developer         = AMD
| manufacturer      = GlobalFoundries
| first announced   = March 7, 2017 
| first launched    = 
| isa               = x86-64
| microarch         = Zen
| word              = 64 bit
| proc              = 14 nm
| tech              = CMOS
| clock min         = 
| clock max         = 
| package           = FCLGA-4094
| socket            = Socket SP3

| succession       = Yes
| predecessor      = 
| predecessor link = 
| successor        = Rome
| successor link   = amd/cores/rome
}}
'''Naples''' is the name of the cores for [[AMD]]'s highest-performance enterprise-level server [[multiprocessors]] based on the {{amd|Zen|l=arch}} microarchitecture. Naples processors support up [[32 cores]] and are fabricated on GlobalFoundries' [[14 nm process]]. Naples-based processors are branded as {{amd|EPYC}}.

Naples processors are set to be introduced in the 2nd quarter of 2017.

== Overview ==
[[File:amd naples 2 sock.jpg|right|thumb]]
AMD Naples [[system on chips]] are a series of high-performance [[multiprocessors]] designed by [[AMD]] based on their {{amd|Zen|l=arch}} microarchitecture. Naples SoCs support both single and 2-way multiprocessing with up to a maximum of 32 cores (and 64 threads) per processor for a total of up to 64 cores (and 128 threads) for a 2-way MP system. Those SoCs sports 128 PCIe lanes each, however half of them are lost when in 2-way MP (leaving the system with the same overall lanes count as a single socket solution). Communication between the two chips is done via AMD's {{amd|Infinity Fabric}} protocol over the 64 [[PCIe]] reserved lanes.

=== Common Features ===
All Naples processors have the following:
* Octa-channel Memory
** Up to DDR4-2400 ECC
** Up to 2 [[TiB]] (4 TiB in 2MP)
* Up to 32 cores / 64 threads
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}



== Naples Processors ==
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           This table is generated automatically from the data in the actual articles.
           If a microprocessor is missing from the list, an appropriate article for it needs to be
           created and tagged accordingly.

           Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
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{{comp table start}}
<table class="comptable sortable tc12 tc13">
<tr class="comptable-header"><th>&nbsp;</th><th colspan="12">List of Naples Processors</th></tr>
<tr class="comptable-header"><th>&nbsp;</th><th colspan="10">Processor</th></tr>
{{comp table header 1|cols=Family, Price, Launched, Cores, Threads, Frequency, Turbo, TDP}}
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]] [[core name::Naples]] 
 |?full page name
 |?model number
 |?microprocessor family
 |?release price
 |?first launched
 |?core count
 |?thread count
 |?base frequency#GHz
 |?turbo frequency (1 core)#GHz
 |?tdp
 |format=template
 |template=proc table 3
 |userparam=10
 |mainlabel=-
 |valuesep=,
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microprocessor family::EPYC]]  [[core name::Naples]]}}
</table>
{{comp table end}}

== See also ==
* {{amd|Zen|l=arch}}
** {{amd|Summit Ridge|l=core}}
* {{intel|Skylake|l=arch}}
** {{intel|Skylake SP|l=core}}
back image	+
designer	AMD +
first announced	March 7, 2017 +
first launched	June 20, 2017 +
instance of	core +
isa	x86-64 +
main image	+
main image caption	Package, front +
manufacturer	GlobalFoundries +
microarchitecture	Zen +
name	Naples +
package	FCLGA-4094 + and SP3 +
process	14 nm (0.014 μm, 1.4e-5 mm) +
socket	LGA-4094 + and SP3 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +