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|microarch=Zen 2 | |microarch=Zen 2 | ||
|chipset=TRX40 | |chipset=TRX40 | ||
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|word=64 bit | |word=64 bit | ||
|proc=7 nm | |proc=7 nm | ||
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|tech=CMOS | |tech=CMOS | ||
− | |clock min= | + | |clock min=3,700 MHz |
− | |clock max= | + | |clock max=3,800 MHz |
− | |package name 1=amd, | + | |package name 1=amd,socket_trx4 |
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|predecessor=Colfax | |predecessor=Colfax | ||
|predecessor link=amd/cores/colfax | |predecessor link=amd/cores/colfax | ||
− | |successor= | + | |successor=Genesis Peak |
− | |successor link=amd/cores/ | + | |successor link=amd/cores/genesis_peak |
}} | }} | ||
− | '''Castle Peak''' ('''CPK | + | '''Castle Peak''' ('''CPK''') is codename for [[AMD]]'s highest-performance enthusiasts [[microprocessors]] serving as a successor to {{\\|Colfax}}, released in late 2019. Castle Peak-based processors are based on the {{amd|Zen 2|l=arch}} microarchitecture and are fabricated on [[TSMC]] [[7 nm process]]. |
Castle Peak-based microprocessors are branded as 3rd-generation [[Ryzen Threadripper]]. | Castle Peak-based microprocessors are branded as 3rd-generation [[Ryzen Threadripper]]. | ||
+ | |||
== Overview == | == Overview == | ||
− | Castle Peak chips are a series of high-performance desktop processors designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. | + | Castle Peak chips are a series of high-performance desktop processors designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. Those processors have 64 PCIe lanes with 8 permanently reserved for the chipset and the other 56 generally set up as 48 lanes for GPUs/accelerators and 4+4 for I/O. |
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− | + | The TRX40 chipset specifications are almost identical to that of the AM4 counterparts, with the key difference being a CPU link of 8 lanes instead of 4, and as a result only 8 dedicated general purpose lanes from the chipset remains. The two banks of 4 PCIe/SATA switchable lanes still remain however, for a total of 16 extra lanes from the chipset, for a total available 4.0 spec lane count of 72, if only 4 SATA ports are required. | |
=== Common Features === | === Common Features === | ||
All Castle Peak processors have the following: | All Castle Peak processors have the following: | ||
+ | * 64 PCIe lanes | ||
+ | * Quad-channel Memory | ||
+ | ** Up to DDR4-3200 ECC | ||
+ | ** Up to ? [[TiB]] | ||
* Up to 64 cores / 128 threads | * Up to 64 cores / 128 threads | ||
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | * Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}} | ||
− | + | == Castle Peak Processors == | |
− | + | <!-- NOTE: | |
− | + | This table is generated automatically from the data in the actual articles. | |
− | + | If a microprocessor is missing from the list, an appropriate article for it needs to be | |
− | + | created and tagged accordingly. | |
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− | + | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips | |
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− | Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
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{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable"> | + | <table class="comptable sortable tc5 tc6"> |
− | {{comp table header|cols|Family| | + | {{comp table header|main|10:List of Castle Peak Processors}} |
+ | {{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}} | ||
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]] | {{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]] | ||
− | |?full page name | + | |?full page name |
− | |?model number | + | |?model number |
− | |?microprocessor family | + | |?microprocessor family |
− | |? | + | |?release price |
− | |?core count | + | |?first launched |
− | |?thread count | + | |?core count |
− | |?l2$ size | + | |?thread count |
− | |?l3$ size | + | |?tdp |
− | |?base frequency#GHz | + | |?l2$ size |
− | |?turbo frequency#GHz | + | |?l3$ size |
− | + | |?base frequency#GHz | |
− | + | |?turbo frequency#GHz | |
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− | + | |template=proc table 3 | |
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− | |template=proc table 3 | ||
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− | |valuesep=, | ||
}} | }} | ||
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}} | {{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}} | ||
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{{clear}} | {{clear}} | ||
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== See also == | == See also == | ||
{{amd zen 2 core see also}} | {{amd zen 2 core see also}} |
Facts about "Castle Peak - Cores - AMD"
chipset | TRX40 + and WRX80 + |
designer | AMD + |
first announced | November 7, 2019 + |
first launched | November 25, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture | Zen 2 + |
name | Castle Peak + |
package | sTRX4 +, sWRX8 + and FCLGA-4094 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) + |
socket | sTRX4 + and sWRX8 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |