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|microarch=Zen 2
 
|microarch=Zen 2
 
|chipset=TRX40
 
|chipset=TRX40
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|chipset 2=WRX80
 
 
|word=64 bit
 
|word=64 bit
 
|proc=7 nm
 
|proc=7 nm
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|proc 2=12 nm
 
 
|tech=CMOS
 
|tech=CMOS
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|clock min=2,700 MHz
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|clock min=3,700 MHz
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|clock max=4,000 MHz
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|clock max=3,800 MHz
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|package name 1=amd,strx4
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|package name 1=amd,socket_trx4
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|package name 2=amd,swrx8
 
 
|predecessor=Colfax
 
|predecessor=Colfax
 
|predecessor link=amd/cores/colfax
 
|predecessor link=amd/cores/colfax
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|successor=Chagall
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|successor=Genesis Peak
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|successor link=amd/cores/chagall
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|successor link=amd/cores/genesis_peak
 
}}
 
}}
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'''Castle Peak''' ('''CPK'''/'''CPKWS''') is the codename for [[AMD]]'s highest-performance enthusiasts [[microprocessors]] serving as a successor to {{\\|Colfax}}, released in late 2019. Castle Peak-based processors are based on the {{amd|Zen 2|l=arch}} microarchitecture and are fabricated on a [[TSMC]] [[7 nm process]].
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'''Castle Peak''' ('''CPK''') is codename for [[AMD]]'s highest-performance enthusiasts [[microprocessors]] serving as a successor to {{\\|Colfax}}, released in late 2019. Castle Peak-based processors are based on the {{amd|Zen 2|l=arch}} microarchitecture and are fabricated on [[TSMC]] [[7 nm process]].
  
 
Castle Peak-based microprocessors are branded as 3rd-generation [[Ryzen Threadripper]].
 
Castle Peak-based microprocessors are branded as 3rd-generation [[Ryzen Threadripper]].
 +
  
 
== Overview ==
 
== Overview ==
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Castle Peak chips are a series of high-performance desktop processors designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture.
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Castle Peak chips are a series of high-performance desktop processors designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture. Those processors have 72 PCIe lanes with 8 permanently reserved for the chipset and the other 64 generally set up as 48 lanes for GPUs/accelerators and 16 for I/O.
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=== Input/Output Interfaces ===
 
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"Castle Peak" processors integrate eight PCIe controllers and four SATA controllers. Workstation (-WX) models have eight 16-lane PCIe Gen 1, 2, 3, 4 (16 GT/s) interfaces, each configurable as up to eight x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) links, so 128 lanes total. Some of these lanes are configurable as SATA Gen 1, 2, 3 (6 Gb/s) link. Up to 32 SATA ports are available from the processor in total, as well as four USB 3.2 Gen [[wikipedia:USB 3.0#USB 3.2|2×1]] (10 Gb/s) ports, and various low speed interfaces. For details see {{amd|Socket sWRX8|l=pack}}.
 
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On "Castle Peak" {{abbr|HEDT}} processors only one half of these PCIe and SATA resources are available, i.e. 64 PCIe lanes on four 16-lane interfaces and up to 16 SATA ports in total. For details see {{amd|Socket sTRX4|l=pack}}.
 
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On Socket sTRX4 and sWRX8 motherboards the PCIe interfaces are generally used for x8 and x16 (electrically) PCIe slots and x4 M.2 NVMe/SATA SSD connectors, leveraging few of the CPU's SATA ports. One x8 PCIe link on the processor is reserved to attach the AMD {{amd|TRX40}} (HEDT) or {{amd|WRX80}} (workstation) chipset which serves as I/O expander. These devices are members of the AMD-500 Series along with the {{amd|X570}} chipset for {{amd|Socket AM4|l=pack}} processors. A notable difference are four additional PCIe lanes available on the X570 as that chipset is attached with an x4 link.
 
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Both the TRX40 and WRX80 offer 16 lanes (plus 8-lane CPU link) PCIe Gen 1, 2, 3, 4; 12 SATA Gen 1, 2, 3 ports, eight sharing pins with the PCIe interface and four dedicated; eight USB 3.2 Gen 2 (10 Gb/s) ports, and four (TRX40) or five (WRX80) USB 2.0 ports. The chipset PCIe interfaces are generally used for PCIe slots, on-board Ethernet controllers, M.2 NVMe/SATA SSD and M.2 WLAN connectors. An audio interface is not provided by the processor or the chipsets, an audio controller is commonly attached as on-board USB device. The sTRX4/TRX40 platform supports overclocking, the sWRX8/WRX80 platform does not.
 
  
 
=== Common Features ===
 
=== Common Features ===
 
All Castle Peak processors have the following:
 
All Castle Peak processors have the following:
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* 64 PCIe lanes
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* Quad-channel Memory
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** Up to DDR4-3200 ECC
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** Up to ? [[TiB]]
 
* Up to 64 cores / 128 threads
 
* Up to 64 cores / 128 threads
 
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
 
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
  
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HEDT processors:
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== Castle Peak Processors ==
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* 64 PCIe lanes
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<!-- NOTE:  
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* Quad-channel Memory
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          This table is generated automatically from the data in the actual articles.
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* Up to DDR4-3200 ECC
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          If a microprocessor is missing from the list, an appropriate article for it needs to be
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* Up to 256&nbsp;GiB using eight 32&nbsp;GiB {{abbr|UDIMM}}s (up to 1&nbsp;TiB/channel addressable)<!--AMD-56443-0.92 Table 2-->
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          created and tagged accordingly.
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Workstation processors:
 
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* 128 PCIe lanes
 
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* Octa-channel Memory
 
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* Up to DDR4-3200 ECC
 
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* Up to 2&nbsp;TiB using eight 256&nbsp;GiB {{abbr|LRDIMM}}s or {{abbr|3DS DIMM}}s (up to 1&nbsp;TiB/channel addressable)<!--ibid.-->
 
  
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== Castle Peak Processors ==
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          Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
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<!-- NOTE:
 
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This table is generated automatically from the data in the actual articles.
 
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If a microprocessor is missing from the list, an appropriate article for it needs to be
 
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created and tagged accordingly.
 
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Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
 
 
-->
 
-->
 
{{comp table start}}
 
{{comp table start}}
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<table class="comptable sortable">
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<table class="comptable sortable tc5 tc6">
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{{comp table header|cols|Family|Microarch.|Cores|Threads|L2$|L3$|Base|Turbo|Memory|{{abbr|TDP}}|Socket|Launched|Price|{{abbr|OPN}}}}
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{{comp table header|main|10:List of Castle Peak Processors}}
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{{comp table header|cols|Family|Price|Launched|Cores|Threads|TDP|L2$|L3$|Base|Turbo}}
 
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
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|?full page name
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|?full page name
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|?model number
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|?model number
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|?microprocessor family
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|?microprocessor family
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|?microarchitecture
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|?release price
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|?core count
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|?first launched
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|?thread count
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|?core count
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|?l2$ size
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|?thread count
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|?l3$ size
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|?tdp
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|?base frequency#GHz
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|?l2$ size
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|?turbo frequency#GHz
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|?l3$ size
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|?supported memory type
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|?base frequency#GHz
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|?tdp
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|?turbo frequency#GHz
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|?package
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|format=template
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|?first launched
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|template=proc table 3
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|?release price
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|userparam=12
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|?part number
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|mainlabel=-
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|sort=model number
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|valuesep=,
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|format=template
 
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|template=proc table 3
 
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|userparam=16
 
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|mainlabel=-
 
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|valuesep=,<br/>
 
 
}}
 
}}
 
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}}
 
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}}
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{{clear}}
 
{{clear}}
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== Bibliography ==
 
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* [https://www.amd.com/en/chipsets/str40 "TRX40 Motherboards for 3rd Gen Ryzen™ Threadripper™ processors"] AMD.com.
 
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* [https://www.amd.com/en/chipsets/wrx80 "Socket sWRX WRX80 Motherboards"] AMD.com.
 
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* {{cite techdoc|title=Infrastructure Roadmap for sTRX4 and sWRX8 Processors|publ=AMD|pid=56443|rev=0.92|date=2021-07}}
 
  
 
== See also ==
 
== See also ==
 
{{amd zen 2 core see also}}
 
{{amd zen 2 core see also}}

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Facts about "Castle Peak - Cores - AMD"
RDF feed
chipsetTRX40 + and WRX80 +
designerAMD +
first announcedNovember 7, 2019 +
first launchedNovember 25, 2019 +
instance ofcore +
isax86-64 +
isa familyx86 +
manufacturerTSMC + and GlobalFoundries +
microarchitectureZen 2 +
nameCastle Peak +
packagesTRX4 +, sWRX8 + and FCLGA-4094 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +
socketsTRX4 + and sWRX8 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +