Editing amd/cores/castle peak

{{amd title|Castle Peak|core}}
{{core
|name=Castle Peak
|no image=Yes
|developer=AMD
|manufacturer=TSMC
|manufacturer 2=GlobalFoundries
|first announced=November 7, 2019
|first launched=November 25, 2019
|isa=x86-64
|isa family=x86
|microarch=Zen 2
|chipset=TRX40
|chipset 2=WRX80
|word=64 bit
|proc=7 nm
|proc 2=12 nm
|tech=CMOS
|clock min=2,700 MHz
|clock max=4,000 MHz
|package module 1={{packages/amd/socket strx4}}
|package module 2={{packages/amd/socket swrx8}}
|predecessor=Colfax
|predecessor link=amd/cores/colfax
|successor=Chagall
|successor link=amd/cores/chagall
}}
'''Castle Peak''' ('''CPK'''/'''CPKWS''') is the codename for [[AMD]]'s highest-performance enthusiasts [[microprocessors]] serving as a successor to {{\\|Colfax}}, released in late 2019. Castle Peak-based processors are based on the {{amd|Zen 2|l=arch}} microarchitecture and are fabricated on a [[TSMC]] [[7 nm process]].

Castle Peak-based microprocessors are branded as 3rd-generation [[Ryzen Threadripper]].

== Overview ==
Castle Peak chips are a series of high-performance desktop processors designed by [[AMD]] based on their {{amd|Zen 2|l=arch}} microarchitecture.

=== Input/Output Interfaces ===
"Castle Peak" processors integrate eight PCIe controllers and four SATA controllers. Workstation (-WX) models have eight 16-lane PCIe Gen 1, 2, 3, 4 (16&nbsp;GT/s) interfaces, each configurable as up to eight x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) links, so 128 lanes total. Some of these lanes are configurable as SATA Gen 1, 2, 3 (6&nbsp;Gb/s) link. Up to 32 SATA ports are available from the processor in total, as well as four USB 3.2 Gen [[wikipedia:USB 3.0#USB 3.2|2×1]] (10&nbsp;Gb/s) ports, and various low speed interfaces. For details see {{amd|Socket sWRX8|l=pack}}.

On "Castle Peak" {{abbr|HEDT}} processors only one half of these PCIe and SATA resources are available, i.e. 64 PCIe lanes on four 16-lane interfaces and up to 16 SATA ports in total. For details see {{amd|Socket sTRX4|l=pack}}.

On Socket sTRX4 and sWRX8 motherboards the PCIe interfaces are generally used for x8 and x16 (electrically) PCIe slots and x4 M.2 NVMe/SATA SSD connectors, leveraging few of the CPU's SATA ports. One x8 PCIe link on the processor is reserved to attach the AMD {{amd|TRX40}} (HEDT) or {{amd|WRX80}} (workstation) chipset which serves as I/O expander. These devices are members of the AMD-500 Series along with the {{amd|X570}} chipset for {{amd|Socket AM4|l=pack}} processors. A notable difference are four additional PCIe lanes available on the X570 as that chipset is attached with an x4 link.

Both the TRX40 and WRX80 offer 16 lanes (plus 8-lane CPU link) PCIe Gen 1, 2, 3, 4; 12 SATA Gen 1, 2, 3 ports, eight sharing pins with the PCIe interface and four dedicated; eight USB 3.2 Gen 2 (10&nbsp;Gb/s) ports, and four (TRX40) or five (WRX80) USB 2.0 ports. The chipset PCIe interfaces are generally used for PCIe slots, on-board Ethernet controllers, M.2 NVMe/SATA SSD and M.2 WLAN connectors. An audio interface is not provided by the processor or the chipsets, an audio controller is commonly attached as on-board USB device. The sTRX4/TRX40 platform supports overclocking, the sWRX8/WRX80 platform does not.

=== Common Features ===
All Castle Peak processors have the following:
* Up to 64 cores / 128 threads
* Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}

HEDT processors:
* 64 PCIe lanes
* Quad-channel Memory
* Up to DDR4-3200 ECC
* Up to 256&nbsp;GiB using eight 32&nbsp;GiB {{abbr|UDIMM}}s (up to 1&nbsp;TiB/channel addressable)<!--AMD-56443-0.92 Table 2-->

Workstation processors:
* 128 PCIe lanes
* Octa-channel Memory
* Up to DDR4-3200 ECC
* Up to 2&nbsp;TiB using eight 256&nbsp;GiB {{abbr|LRDIMM}}s or {{abbr|3DS DIMM}}s (up to 1&nbsp;TiB/channel addressable)<!--ibid.-->

== Castle Peak Processors ==
<!-- NOTE:
This table is generated automatically from the data in the actual articles.
If a microprocessor is missing from the list, an appropriate article for it needs to be
created and tagged accordingly.
Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
-->
{{comp table start}}
<table class="comptable sortable">
{{comp table header|cols|Family|Microarch.|Cores|Threads|L2$|L3$|Base|Turbo|Memory|{{abbr|TDP}}|Socket|Launched|Price|{{abbr|OPN}}}}
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
|?full page name
|?model number
|?microprocessor family
|?microarchitecture
|?core count
|?thread count
|?l2$ size
|?l3$ size
|?base frequency#GHz
|?turbo frequency#GHz
|?supported memory type
|?tdp
|?package
|?first launched
|?release price
|?part number
|sort=model number
|format=template
|template=proc table 3
|userparam=16
|mainlabel=-
|valuesep=,<br/>
}}
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Castle Peak]]}}
</table>
{{comp table end}}

=== SKU Comparison ===
Below are a number of SKU comparison graphs based on their specifications.

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 |?core count
 |?base frequency
 |charttitle=Cores vs. Base Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 |?core count
 |?turbo frequency
 |charttitle=Cores vs. Turbo Frequency
 |numbersaxislabel=Frequency (MHz)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 |?core count
 |?tdp
 |charttitle=Cores vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Core Count
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

<div style="float: left; margin: 10px">
{{#ask: [[Category:microprocessor models by amd]] [[core name::Castle Peak]]
 |?turbo frequency
 |?tdp
 |charttitle=Frequency vs. TDP
 |numbersaxislabel=TDP (W)
 |labelaxislabel=Frequency (MHz)
 |height=400
 |width=400
 |theme=vector
 |group=property
 |grouplabel=subject
 |charttype=scatter
 |format=jqplotseries
 |mainlabel=-
}}
</div>

{{clear}}

== Bibliography ==
* [https://www.amd.com/en/chipsets/str40 "TRX40 Motherboards for 3rd Gen Ryzen™ Threadripper™ processors"] AMD.com.
* [https://www.amd.com/en/chipsets/wrx80 "Socket sWRX WRX80 Motherboards"] AMD.com.
* {{cite techdoc|title=Infrastructure Roadmap for sTRX4 and sWRX8 Processors|publ=AMD|pid=56443|rev=0.92|date=2021-07}}

== See also ==
{{amd zen 2 core see also}}
chipset	TRX40 + and WRX80 +
designer	AMD +
first announced	November 7, 2019 +
first launched	November 25, 2019 +
instance of	core +
isa	x86-64 +
isa family	x86 +
manufacturer	TSMC + and GlobalFoundries +
microarchitecture	Zen 2 +
name	Castle Peak +
package	sTRX4 +, sWRX8 + and FCLGA-4094 +
process	7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +
socket	sTRX4 + and sWRX8 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +