Semiconductor & Computer Engineering
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Difference between revisions of "amd/am486/am486dx4-100sv8b"
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| name = Am486DX4-100SV8B | | name = Am486DX4-100SV8B | ||
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Latest revision as of 15:19, 13 December 2017
| Edit Values | |
| Am486DX4-100SV8B | |
 | |
| Am486DX4-100SV8B | |
| General Info | |
| Designer | AMD |
| Manufacturer | AMD |
| Model Number | Am486DX4-100SV8B |
| Part Number | A80486DX4-100SV8B, S80486DX4-100SV8B |
| Introduction | 1995 (announced) March, 1996 (launched) |
| Shop | Amazon |
| General Specs | |
| Family | Am486 |
| Series | Am486DX4S |
| Frequency | 100 MHz |
| Bus type | FSB |
| Bus speed | 33 MHz |
| Bus rate | 33 MT/s |
| Clock multiplier | 3 |
| Microarchitecture | |
| Microarchitecture | 80486 |
| Core Name | Am486DX4S |
| Process | 500 nm |
| Technology | CMOS |
| Word Size | 32 bit |
| Cores | 1 |
| Max Memory | 4 GiB |
| Multiprocessing | |
| Max SMP | 1-Way (Uniprocessor) |
| Electrical | |
| Vcore | 3.3 V ± 0.3 V |
| OP Temperature | 0 °C – 85 °C |
Am486DX4-100SV8B was an Enhanced Am486 microprocessor introduced by AMD in 1996. This processor had a clock multiplier of 3 having a frequency of 100 MHz with a bus frequency of 33 MHz. This "Enhanced" Am486 includes some other features such as SMM, stop-clock control, and write-back cache. AMD later introduced the Am486DX4-100SV16B which was identical but had its L1$ doubled to 16 KB.
Cache[edit]
- Main article: 80486 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 8 KiB 8,192 B 0.00781 MiB |
1x8 KiB 4-way set associative (unified, write-back policy) |
Graphics[edit]
This chip had no integrated graphics processing unit.
Features[edit]
- Stop-clock control
- System Management Mode (SMM)
Packaging[edit]
| Part | Package |
|---|---|
| A80486DX4-100SV8B | CPGA-168 |
| S80486DX4-100SV8B | SQFP-208 |
Documents[edit]
Gallery[edit]
See also[edit]
Facts about "Am486DX4-100SV8B - AMD"
| has feature | System Management Mode + |
| l1$ description | 4-way set associative + |
| l1$ size | 8 KiB (8,192 B, 0.00781 MiB) + |
